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zhengxiaolinXRealFYang
zhengxiaolinX
authored and
RealFYang
committedSep 29, 2022
8294492: RISC-V: Use li instead of patchable movptr at non-patchable callsites
Reviewed-by: fyang
1 parent 8491fd5 commit 1decdce

8 files changed

+51
-82
lines changed
 

‎src/hotspot/cpu/riscv/assembler_riscv.cpp

-26
Original file line numberDiff line numberDiff line change
@@ -187,30 +187,6 @@ void Assembler::li32(Register Rd, int32_t imm) {
187187

188188
#undef INSN
189189

190-
void Assembler::ret() {
191-
jalr(x0, x1, 0);
192-
}
193-
194-
#define INSN(NAME, REGISTER) \
195-
void Assembler::NAME(const address &dest, Register temp) { \
196-
assert_cond(dest != NULL); \
197-
assert(temp != noreg, "temp must not be empty register!"); \
198-
int64_t distance = dest - pc(); \
199-
if (is_offset_in_range(distance, 32)) { \
200-
auipc(temp, distance + 0x800); \
201-
jalr(REGISTER, temp, ((int32_t)distance << 20) >> 20); \
202-
} else { \
203-
int32_t offset = 0; \
204-
movptr(temp, dest, offset); \
205-
jalr(REGISTER, temp, offset); \
206-
} \
207-
}
208-
209-
INSN(call, x1);
210-
INSN(tail, x0);
211-
212-
#undef INSN
213-
214190
#define INSN(NAME, REGISTER) \
215191
void Assembler::NAME(const Address &adr, Register temp) { \
216192
switch (adr.getMode()) { \
@@ -232,8 +208,6 @@ void Assembler::ret() {
232208

233209
INSN(j, x0);
234210
INSN(jal, x1);
235-
INSN(call, x1);
236-
INSN(tail, x0);
237211

238212
#undef INSN
239213

‎src/hotspot/cpu/riscv/assembler_riscv.hpp

+2-12
Original file line numberDiff line numberDiff line change
@@ -302,7 +302,8 @@ class Assembler : public AbstractAssembler {
302302
lui(Rd, upper);
303303
offset = lower;
304304
} else {
305-
movptr(Rd, (address)(uintptr_t)adr.offset(), offset);
305+
offset = ((int32_t)adr.offset() << 20) >> 20;
306+
li(Rd, adr.offset() - offset);
306307
}
307308
add(Rd, Rd, adr.base());
308309
}
@@ -331,17 +332,6 @@ class Assembler : public AbstractAssembler {
331332
void jal(const Address &adr, Register temp = t0);
332333
void jr(Register Rs);
333334
void jalr(Register Rs);
334-
void ret();
335-
void call(const address &dest, Register temp = t0);
336-
void call(const Address &adr, Register temp = t0);
337-
void tail(const address &dest, Register temp = t0);
338-
void tail(const Address &adr, Register temp = t0);
339-
void call(Label &l, Register temp) {
340-
call(target(l), temp);
341-
}
342-
void tail(Label &l, Register temp) {
343-
tail(target(l), temp);
344-
}
345335

346336
static inline uint32_t extract(uint32_t val, unsigned msb, unsigned lsb) {
347337
assert_cond(msb >= lsb && msb <= 31);

‎src/hotspot/cpu/riscv/gc/shenandoah/shenandoahBarrierSetAssembler_riscv.cpp

+15-13
Original file line numberDiff line numberDiff line change
@@ -282,24 +282,25 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
282282
}
283283

284284
__ push_call_clobbered_registers();
285+
address target = NULL;
285286
if (is_strong) {
286287
if (is_narrow) {
287-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
288+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow);
288289
} else {
289-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
290+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong);
290291
}
291292
} else if (is_weak) {
292293
if (is_narrow) {
293-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow));
294+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow);
294295
} else {
295-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
296+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak);
296297
}
297298
} else {
298299
assert(is_phantom, "only remaining strength");
299300
assert(!is_narrow, "phantom access cannot be narrow");
300-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
301+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak);
301302
}
302-
__ jalr(ra);
303+
__ call(target);
303304
__ mv(t0, x10);
304305
__ pop_call_clobbered_registers();
305306
__ mv(x10, t0);
@@ -679,29 +680,30 @@ void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_s
679680
bool is_weak = ShenandoahBarrierSet::is_weak_access(decorators);
680681
bool is_phantom = ShenandoahBarrierSet::is_phantom_access(decorators);
681682
bool is_native = ShenandoahBarrierSet::is_native_access(decorators);
683+
address target = NULL;
682684
if (is_strong) {
683685
if (is_native) {
684-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
686+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong);
685687
} else {
686688
if (UseCompressedOops) {
687-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
689+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow);
688690
} else {
689-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong));
691+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong);
690692
}
691693
}
692694
} else if (is_weak) {
693695
assert(!is_native, "weak must not be called off-heap");
694696
if (UseCompressedOops) {
695-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow));
697+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak_narrow);
696698
} else {
697-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak));
699+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_weak);
698700
}
699701
} else {
700702
assert(is_phantom, "only remaining strength");
701703
assert(is_native, "phantom must only be called off-heap");
702-
__ mv(ra, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom));
704+
target = CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom);
703705
}
704-
__ jalr(ra);
706+
__ call(target);
705707
__ mv(t0, x10);
706708
__ pop_call_clobbered_registers();
707709
__ mv(x10, t0);

‎src/hotspot/cpu/riscv/macroAssembler_riscv.cpp

+1-3
Original file line numberDiff line numberDiff line change
@@ -563,10 +563,8 @@ void MacroAssembler::emit_static_call_stub() {
563563
void MacroAssembler::call_VM_leaf_base(address entry_point,
564564
int number_of_arguments,
565565
Label *retaddr) {
566-
int32_t offset = 0;
567566
push_reg(RegSet::of(t0, xmethod), sp); // push << t0 & xmethod >> to sp
568-
movptr(t0, entry_point, offset);
569-
jalr(x1, t0, offset);
567+
call(entry_point);
570568
if (retaddr != NULL) {
571569
bind(*retaddr);
572570
}

‎src/hotspot/cpu/riscv/macroAssembler_riscv.hpp

+21-3
Original file line numberDiff line numberDiff line change
@@ -527,12 +527,18 @@ class MacroAssembler: public Assembler {
527527
}
528528

529529
// mv
530-
void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); }
530+
void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); }
531+
void mv(Register Rd, address addr, int32_t &offset) {
532+
// Split address into a lower 12-bit sign-extended offset and the remainder,
533+
// so that the offset could be encoded in jalr or load/store instruction.
534+
offset = ((int32_t)(int64_t)addr << 20) >> 20;
535+
li(Rd, (int64_t)addr - offset);
536+
}
531537

532538
template<typename T, ENABLE_IF(std::is_integral<T>::value)>
533-
inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }
539+
inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }
534540

535-
inline void mvw(Register Rd, int32_t imm32) { mv(Rd, imm32); }
541+
inline void mvw(Register Rd, int32_t imm32) { mv(Rd, imm32); }
536542

537543
void mv(Register Rd, Address dest);
538544
void mv(Register Rd, RegisterOrConstant src);
@@ -890,6 +896,18 @@ class MacroAssembler: public Assembler {
890896

891897
void rt_call(address dest, Register tmp = t0);
892898

899+
void call(const address dest, Register temp = t0) {
900+
assert_cond(dest != NULL);
901+
assert(temp != noreg, "temp must not be empty register!");
902+
int32_t offset = 0;
903+
mv(temp, dest, offset);
904+
jalr(x1, temp, offset);
905+
}
906+
907+
void ret() {
908+
jalr(x0, x1, 0);
909+
}
910+
893911
private:
894912

895913
#ifdef ASSERT

‎src/hotspot/cpu/riscv/stubGenerator_riscv.cpp

+2-6
Original file line numberDiff line numberDiff line change
@@ -651,9 +651,7 @@ class StubGenerator: public StubCodeGenerator {
651651
assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
652652
#endif
653653
BLOCK_COMMENT("call MacroAssembler::debug");
654-
int32_t offset = 0;
655-
__ movptr(t0, CAST_FROM_FN_PTR(address, MacroAssembler::debug64), offset);
656-
__ jalr(x1, t0, offset);
654+
__ call(CAST_FROM_FN_PTR(address, MacroAssembler::debug64));
657655
__ ebreak();
658656

659657
return start;
@@ -3740,9 +3738,7 @@ class StubGenerator: public StubCodeGenerator {
37403738
}
37413739
__ mv(c_rarg0, xthread);
37423740
BLOCK_COMMENT("call runtime_entry");
3743-
int32_t offset = 0;
3744-
__ movptr(t0, runtime_entry, offset);
3745-
__ jalr(x1, t0, offset);
3741+
__ call(runtime_entry);
37463742

37473743
// Generate oop map
37483744
OopMap* map = new OopMap(framesize, 0);

‎src/hotspot/cpu/riscv/templateInterpreterGenerator_riscv.cpp

+9-18
Original file line numberDiff line numberDiff line change
@@ -190,8 +190,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
190190
} else {
191191
fn = CAST_FROM_FN_PTR(address, StubRoutines::dsin());
192192
}
193-
__ mv(t0, fn);
194-
__ jalr(t0);
193+
__ call(fn);
195194
break;
196195
case Interpreter::java_lang_math_cos :
197196
entry_point = __ pc();
@@ -204,8 +203,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
204203
} else {
205204
fn = CAST_FROM_FN_PTR(address, StubRoutines::dcos());
206205
}
207-
__ mv(t0, fn);
208-
__ jalr(t0);
206+
__ call(fn);
209207
break;
210208
case Interpreter::java_lang_math_tan :
211209
entry_point = __ pc();
@@ -218,8 +216,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
218216
} else {
219217
fn = CAST_FROM_FN_PTR(address, StubRoutines::dtan());
220218
}
221-
__ mv(t0, fn);
222-
__ jalr(t0);
219+
__ call(fn);
223220
break;
224221
case Interpreter::java_lang_math_log :
225222
entry_point = __ pc();
@@ -232,8 +229,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
232229
} else {
233230
fn = CAST_FROM_FN_PTR(address, StubRoutines::dlog());
234231
}
235-
__ mv(t0, fn);
236-
__ jalr(t0);
232+
__ call(fn);
237233
break;
238234
case Interpreter::java_lang_math_log10 :
239235
entry_point = __ pc();
@@ -246,8 +242,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
246242
} else {
247243
fn = CAST_FROM_FN_PTR(address, StubRoutines::dlog10());
248244
}
249-
__ mv(t0, fn);
250-
__ jalr(t0);
245+
__ call(fn);
251246
break;
252247
case Interpreter::java_lang_math_exp :
253248
entry_point = __ pc();
@@ -260,8 +255,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
260255
} else {
261256
fn = CAST_FROM_FN_PTR(address, StubRoutines::dexp());
262257
}
263-
__ mv(t0, fn);
264-
__ jalr(t0);
258+
__ call(fn);
265259
break;
266260
case Interpreter::java_lang_math_pow :
267261
entry_point = __ pc();
@@ -275,8 +269,7 @@ address TemplateInterpreterGenerator::generate_math_entry(AbstractInterpreter::M
275269
} else {
276270
fn = CAST_FROM_FN_PTR(address, StubRoutines::dpow());
277271
}
278-
__ mv(t0, fn);
279-
__ jalr(t0);
272+
__ call(fn);
280273
break;
281274
case Interpreter::java_lang_math_fmaD :
282275
if (UseFMA) {
@@ -1169,8 +1162,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
11691162
// hand.
11701163
//
11711164
__ mv(c_rarg0, xthread);
1172-
__ mv(t1, CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans));
1173-
__ jalr(t1);
1165+
__ call(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans));
11741166
__ get_method(xmethod);
11751167
__ reinit_heapbase();
11761168
__ bind(Continue);
@@ -1219,8 +1211,7 @@ address TemplateInterpreterGenerator::generate_native_entry(bool synchronized) {
12191211

12201212
__ push_call_clobbered_registers();
12211213
__ mv(c_rarg0, xthread);
1222-
__ mv(t1, CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
1223-
__ jalr(t1);
1214+
__ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
12241215
__ pop_call_clobbered_registers();
12251216
__ bind(no_reguard);
12261217
}

‎src/hotspot/cpu/riscv/templateTable_riscv.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -387,7 +387,7 @@ void TemplateTable::fast_aldc(bool wide) {
387387

388388
// Stash null_sentinel address to get its value later
389389
int32_t offset = 0;
390-
__ movptr(rarg, Universe::the_null_sentinel_addr(), offset);
390+
__ mv(rarg, Universe::the_null_sentinel_addr(), offset);
391391
__ ld(tmp, Address(rarg, offset));
392392
__ resolve_oop_handle(tmp, x15, t1);
393393
__ bne(result, tmp, notNull);

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 (1)

openjdk-notifier[bot] commented on Sep 29, 2022

@openjdk-notifier[bot]
openjdk-notifier[bot]
on Sep 29, 2022

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