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8320807: [PPC64][ZGC] C1 generates wrong code for atomics #16835

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8320807: [PPC64][ZGC] C1 generates wrong code for atomics #16835

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[PPC64][ZGC] C1 generates wrong code for atomics
TheRealMDoerr Nov 27, 2023
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TheRealMDoerr Dec 1, 2023
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4 changes: 2 additions & 2 deletions src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
View file
Original file line number Diff line number Diff line change
@@ -2600,7 +2600,7 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
Unimplemented();
}

// Volatile load may be followed by Unsafe CAS.
// There might be a volatile load before this Unsafe CAS.
if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ sync();
} else {
@@ -2981,7 +2981,7 @@ void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr
}
}

// Volatile load may be followed by Unsafe OP.
// There might be a volatile load before this Unsafe OP.
if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ sync();
} else {
2 changes: 1 addition & 1 deletion src/hotspot/cpu/ppc/gc/shenandoah/c1/shenandoahBarrierSetC1_ppc.cpp
View file
Original file line number Diff line number Diff line change
@@ -53,7 +53,7 @@ void LIR_OpShenandoahCompareAndSwap::emit_code(LIR_Assembler *masm) {
__ encode_heap_oop(new_val, new_val);
}

// Volatile load may be followed by Unsafe CAS.
// There might be a volatile load before this Unsafe CAS.
if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
__ sync();
} else {