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8333566: Remove unused methods #19550

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8333566: Remove unused methods #19550

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486de92
Remove defined but unused methods.
JohnTortugo May 26, 2024
408a66b
Merge remote-tracking branch 'origin/main' into unused-methods
JohnTortugo Jun 4, 2024
17097b4
Merge remote-tracking branch 'origin/main' into unused-methods
JohnTortugo Jun 5, 2024
5b18baa
Removing unused methods in aarch64
JohnTortugo Jun 6, 2024
97df1b2
Temove trailing whitespace.
JohnTortugo Jun 6, 2024
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19 changes: 0 additions & 19 deletions src/hotspot/cpu/aarch64/assembler_aarch64.hpp
View file
Original file line number Diff line number Diff line change
@@ -183,7 +183,6 @@ class Instruction_aarch64 {

inline ~Instruction_aarch64();

unsigned &get_insn() { return insn; }
#ifdef ASSERT
unsigned &get_bits() { return bits; }
#endif
@@ -2998,15 +2997,6 @@ template<typename R, typename... Rx>
_xshll(/* is_unsigned */ false, Vd, Ta, Vn, Tb, shift);
}

void sshll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
assert(Tb == T16B || Tb == T8H || Tb == T4S, "invalid arrangement");
_xshll(/* is_unsigned */ false, Vd, Ta, Vn, Tb, shift);
}

void sxtl(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb) {
sshll(Vd, Ta, Vn, Tb, 0);
}

// Move from general purpose register
// mov Vd.T[index], Rn
void mov(FloatRegister Vd, SIMD_RegVariant T, int index, Register Xn) {
@@ -3044,15 +3034,6 @@ template<typename R, typename... Rx>
_pmull(Vd, Ta, Vn, Vm, Tb);
}

void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
starti;
int size_b = (int)Tb >> 1;
int size_a = (int)Ta >> 1;
assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
}

void xtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
starti;
int size_b = (int)Tb >> 1;
40 changes: 0 additions & 40 deletions src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp
View file
Original file line number Diff line number Diff line change
@@ -227,7 +227,6 @@ class MacroAssembler: public Assembler {
}
}

inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }

inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
@@ -243,23 +242,10 @@ class MacroAssembler: public Assembler {
bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
}

inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
bfmw(Rd, Rn, lsb, (lsb + width - 1));
}
inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
bfm(Rd, Rn, lsb , (lsb + width - 1));
}

inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
}
inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
}

inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
sbfmw(Rd, Rn, lsb, (lsb + width - 1));
}
inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
sbfm(Rd, Rn, lsb , (lsb + width - 1));
}
@@ -423,9 +409,6 @@ class MacroAssembler: public Assembler {
smaddl(Rd, Rn, Rm, zr);
}

inline void umnegl(Register Rd, Register Rn, Register Rm) {
umsubl(Rd, Rn, Rm, zr);
}
inline void umull(Register Rd, Register Rn, Register Rm) {
umaddl(Rd, Rn, Rm, zr);
}
@@ -571,11 +554,6 @@ class MacroAssembler: public Assembler {
mrs(0b11, 0b0100, 0b0100, 0b001, reg);
}

inline void set_fpsr(Register reg)
{
msr(0b011, 0b0100, 0b0100, 0b001, reg);
}

inline void clear_fpsr()
{
msr(0b011, 0b0100, 0b0100, 0b001, zr);
@@ -594,24 +572,6 @@ class MacroAssembler: public Assembler {
msr(0b011, 0b0100, 0b0100, 0b000, reg);
}

// DCZID_EL0: op1 == 011
// CRn == 0000
// CRm == 0000
// op2 == 111
inline void get_dczid_el0(Register reg)
{
mrs(0b011, 0b0000, 0b0000, 0b111, reg);
}

// CTR_EL0: op1 == 011
// CRn == 0000
// CRm == 0000
// op2 == 001
inline void get_ctr_el0(Register reg)
{
mrs(0b011, 0b0000, 0b0000, 0b001, reg);
}

inline void get_nzcv(Register reg) {
mrs(0b011, 0b0100, 0b0010, 0b000, reg);
}
3 changes: 0 additions & 3 deletions src/hotspot/cpu/aarch64/vm_version_aarch64.hpp
View file
Original file line number Diff line number Diff line change
@@ -148,9 +148,6 @@ enum Ampere_CPU_Model {

static int cpu_family() { return _cpu; }
static int cpu_model() { return _model; }
static int cpu_model2() { return _model2; }
static int cpu_variant() { return _variant; }
static int cpu_revision() { return _revision; }

static bool model_is(int cpu_model) {
return _model == cpu_model || _model2 == cpu_model;
10 changes: 0 additions & 10 deletions src/hotspot/cpu/arm/assembler_arm_32.hpp
View file
Original file line number Diff line number Diff line change
@@ -317,11 +317,6 @@ class Assembler : public AbstractAssembler {
rn->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding());
}

void mlas(Register rd, Register rm, Register rs, Register rn, AsmCondition cond = al) {
emit_int32(cond << 28 | 1 << 21 | 1 << 20 | rd->encoding() << 16 |
rn->encoding() << 12 | rs->encoding() << 8 | 0x9 << 4 | rm->encoding());
}

// Loads and stores

#define F(mnemonic, l, b) \
@@ -584,11 +579,6 @@ class Assembler : public AbstractAssembler {
F(bl, 0xb)
#undef F

void udf(int imm_16) {
assert((imm_16 >> 16) == 0, "encoding constraint");
emit_int32(0xe7f000f0 | (imm_16 & 0xfff0) << 8 | (imm_16 & 0xf));
}

// ARMv7 instructions

#define F(mnemonic, wt) \
1 change: 0 additions & 1 deletion src/hotspot/cpu/arm/interp_masm_arm.hpp
View file
Original file line number Diff line number Diff line change
@@ -66,7 +66,6 @@ class InterpreterMacroAssembler: public MacroAssembler {
inline void check_stack_top() {}
inline void check_stack_top_on_expansion() {}
inline void check_extended_sp(Register tmp) {}
inline void check_no_cached_stack_top(Register tmp) {}

void save_bcp() { str(Rbcp, Address(FP, frame::interpreter_frame_bcp_offset * wordSize)); }
void restore_bcp() { ldr(Rbcp, Address(FP, frame::interpreter_frame_bcp_offset * wordSize)); }
13 changes: 0 additions & 13 deletions src/hotspot/cpu/arm/macroAssembler_arm.hpp
View file
Original file line number Diff line number Diff line change
@@ -440,15 +440,6 @@ class MacroAssembler: public Assembler {
void should_not_reach_here() { stop("should not reach here"); }
static void debug(const char* msg, const intx* registers);

// Create a walkable frame to help tracking down who called this code.
// Returns the frame size in words.
int should_not_call_this() {
raw_push(FP, LR);
should_not_reach_here();
flush();
return 2; // frame_size_in_words (FP+LR)
}

int save_all_registers();
void restore_all_registers();
int save_caller_save_registers();
@@ -756,10 +747,6 @@ class MacroAssembler: public Assembler {
mov(dst, AsmOperand(src, lsr, shift));
}

void arith_shift_right(Register dst, Register src, int shift) {
mov(dst, AsmOperand(src, asr, shift));
}

void asr_32(Register dst, Register src, int shift) {
mov(dst, AsmOperand(src, asr, shift));
}
14 changes: 0 additions & 14 deletions src/hotspot/cpu/arm/nativeInst_arm_32.hpp
View file
Original file line number Diff line number Diff line change
@@ -65,14 +65,6 @@ class RawNativeInstruction {
// permanently undefined (UDF): 0xe << 28 | 0b1111111 << 20 | 0b1111 << 4
static const int not_entrant_illegal_instruction = 0xe7f000f0;

static int decode_rotated_imm12(int encoding) {
int base = encoding & 0xff;
int right_rotation = (encoding & 0xf00) >> 7;
int left_rotation = 32 - right_rotation;
int val = (base >> right_rotation) | (base << left_rotation);
return val;
}

address addr_at(int offset) const { return (address)this + offset; }
address instruction_address() const { return addr_at(0); }
address next_raw_instruction_address() const { return addr_at(instruction_size); }
@@ -106,17 +98,12 @@ class RawNativeInstruction {
bool is_b() const { return (encoding() & 0x0f000000) == 0x0a000000; }
bool is_bx() const { return (encoding() & 0x0ffffff0) == 0x012fff10; }
bool is_bl() const { return (encoding() & 0x0f000000) == 0x0b000000; }
bool is_blx() const { return (encoding() & 0x0ffffff0) == 0x012fff30; }
bool is_fat_call() const {
return (is_add_lr() && next_raw()->is_jump());
}
bool is_ldr_call() const {
return (is_add_lr() && next_raw()->is_ldr_pc());
}
bool is_jump() const { return is_b() || is_ldr_pc(); }
bool is_call() const { return is_bl() || is_fat_call(); }
bool is_branch() const { return is_b() || is_bl(); }
bool is_far_branch() const { return is_movw() || is_ldr_literal(); }
bool is_ldr_literal() const {
// ldr Rx, [PC, #offset] for positive or negative offsets
return (encoding() & 0x0f7f0000) == 0x051f0000;
@@ -145,7 +132,6 @@ class RawNativeInstruction {
bool is_sub_pc() const { return (encoding() & 0x0fff0000) == 0x024f0000; }
bool is_pc_rel() const { return is_add_pc() || is_sub_pc(); }
bool is_movw() const { return (encoding() & 0x0ff00000) == 0x03000000; }
bool is_movt() const { return (encoding() & 0x0ff00000) == 0x03400000; }
// c2 doesn't use fixed registers for safepoint poll address
bool is_safepoint_poll() const { return (encoding() & 0xfff0ffff) == 0xe590c000; }
};
2 changes: 0 additions & 2 deletions src/hotspot/cpu/arm/vm_version_arm.hpp
View file
Original file line number Diff line number Diff line change
@@ -102,8 +102,6 @@ class VM_Version: public Abstract_VM_Version {

static bool simd_math_is_compliant() { return false; }

static bool prefer_moves_over_load_literal() { return supports_movw(); }

friend class VM_Version_StubGenerator;

static void initialize_cpu_information(void);
53 changes: 0 additions & 53 deletions src/hotspot/cpu/ppc/assembler_ppc.hpp
View file
Original file line number Diff line number Diff line change
@@ -1028,11 +1028,6 @@ class Assembler : public AbstractAssembler {
"value out of range");
}

static void assert_signed_word_disp_range(intptr_t x, int nbits) {
assert((x & 3) == 0, "not word aligned");
assert_signed_range(x, nbits + 2);
}

static void assert_unsigned_const(int x, int nbits) {
assert(juint(x) < juint(1 << nbits), "unsigned constant out of range");
}
@@ -1107,20 +1102,6 @@ class Assembler : public AbstractAssembler {
static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); }
static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); }

// For extended opcodes (prefixed instructions) introduced with Power 10
static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); }
static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); }
static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); }
static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); }

// - 8LS:D/MLS:D Formats
static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); }

// - 8RR:XX4/8RR:D Formats
static long inv_imm0_eo(int x) { return inv_opp_u_field(x, 31, 16); }
static long inv_uimm_eo(int x) { return inv_opp_u_field(x, 31, 29); }
static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); }

#define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit))
#define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit))

@@ -1142,7 +1123,6 @@ class Assembler : public AbstractAssembler {
static int d1( int x) { return opp_s_field(x, 31, 16); }
static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); }
static int eh( int x) { return opp_u_field(x, 31, 31); }
static int flm( int x) { return opp_u_field(x, 14, 7); }
static int fra( FloatRegister r) { return fra(r->encoding());}
static int frb( FloatRegister r) { return frb(r->encoding());}
static int frc( FloatRegister r) { return frc(r->encoding());}
@@ -1245,29 +1225,14 @@ class Assembler : public AbstractAssembler {
// For extended opcodes (prefixed instructions) introduced with Power 10
static long r_eo( int x) { return opp_u_field(x, 11, 11); }
static long type( int x) { return opp_u_field(x, 7, 6); }
static long st_x0( int x) { return opp_u_field(x, 8, 8); }
static long st_x1( int x) { return opp_u_field(x, 11, 8); }

// - 8LS:D/MLS:D Formats
static long d0_eo( long x) { return opp_u_field((x >> 16) & 0x3FFFF, 31, 14); }
static long d1_eo( long x) { return opp_u_field(x & 0xFFFF, 31, 16); }
static long s0_eo( long x) { return d0_eo(x); }
static long s1_eo( long x) { return d1_eo(x); }

// - 8RR:XX4/8RR:D Formats
static long imm0_eo( int x) { return opp_u_field(x >> 16, 31, 16); }
static long imm1_eo( int x) { return opp_u_field(x & 0xFFFF, 31, 16); }
static long uimm_eo( int x) { return opp_u_field(x, 31, 29); }
static long imm_eo( int x) { return opp_u_field(x, 31, 24); }

//static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes
//static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes
//static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes
//static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes
//static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes
//static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes
//static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes

protected:
// Compute relative address for branch.
static intptr_t disp(intptr_t x, intptr_t off) {
@@ -1300,9 +1265,6 @@ class Assembler : public AbstractAssembler {
return (short)((int *)a)[instruction_number];
}

static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); }
static inline int lo16_unsigned(int x) { return x & 0xffff; }

protected:

// Extract the top 32 bits in a 64 bit word.
@@ -1475,9 +1437,6 @@ class Assembler : public AbstractAssembler {
static bool is_bcxx(int x) {
return BCXX_OPCODE == (x & BCXX_OPCODE_MASK);
}
static bool is_bxx_or_bcxx(int x) {
return is_bxx(x) || is_bcxx(x);
}
static bool is_bctrl(int x) {
return x == 0x4e800421;
}
@@ -1508,24 +1467,12 @@ class Assembler : public AbstractAssembler {
static bool is_stdu(int x) {
return STDU_OPCODE == (x & STDU_OPCODE_MASK);
}
static bool is_stdx(int x) {
return STDX_OPCODE == (x & STDX_OPCODE_MASK);
}
static bool is_stdux(int x) {
return STDUX_OPCODE == (x & STDUX_OPCODE_MASK);
}
static bool is_stwx(int x) {
return STWX_OPCODE == (x & STWX_OPCODE_MASK);
}
static bool is_stwux(int x) {
return STWUX_OPCODE == (x & STWUX_OPCODE_MASK);
}
static bool is_stw(int x) {
return STW_OPCODE == (x & STW_OPCODE_MASK);
}
static bool is_stwu(int x) {
return STWU_OPCODE == (x & STWU_OPCODE_MASK);
}
static bool is_ori(int x) {
return ORI_OPCODE == (x & ORI_OPCODE_MASK);
};
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