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Yi-Fan TsaiPaul Hohensee
Yi-Fan Tsai
authored and
Paul Hohensee
committedSep 6, 2022
8288445: AArch64: C2 compilation fails with guarantee(!true || (true && (shift != 0))) failed: impossible encoding
Reviewed-by: phh Backport-of: b4490386fe348250e88347526172c1c27ef01eba
1 parent c4721bc commit 328ea9d

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4 files changed

+115
-32
lines changed

4 files changed

+115
-32
lines changed
 

‎src/hotspot/cpu/aarch64/aarch64.ad

+10
Original file line numberDiff line numberDiff line change
@@ -4295,6 +4295,16 @@ operand immI_65535()
42954295
interface(CONST_INTER);
42964296
%}
42974297

4298+
operand immI_positive()
4299+
%{
4300+
predicate(n->get_int() > 0);
4301+
match(ConI);
4302+
4303+
op_cost(0);
4304+
format %{ %}
4305+
interface(CONST_INTER);
4306+
%}
4307+
42984308
operand immL_255()
42994309
%{
43004310
predicate(n->get_long() == 255L);

‎src/hotspot/cpu/aarch64/aarch64_neon.ad

+28-28
Original file line numberDiff line numberDiff line change
@@ -4428,7 +4428,7 @@ instruct vsll16B_imm(vecX dst, vecX src, immI shift) %{
44284428
ins_pipe(vshift128_imm);
44294429
%}
44304430

4431-
instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
4431+
instruct vsra8B_imm(vecD dst, vecD src, immI_positive shift) %{
44324432
predicate(n->as_Vector()->length() == 4 ||
44334433
n->as_Vector()->length() == 8);
44344434
match(Set dst (RShiftVB src (RShiftCntV shift)));
@@ -4443,7 +4443,7 @@ instruct vsra8B_imm(vecD dst, vecD src, immI shift) %{
44434443
ins_pipe(vshift64_imm);
44444444
%}
44454445

4446-
instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
4446+
instruct vsra16B_imm(vecX dst, vecX src, immI_positive shift) %{
44474447
predicate(n->as_Vector()->length() == 16);
44484448
match(Set dst (RShiftVB src (RShiftCntV shift)));
44494449
ins_cost(INSN_COST);
@@ -4457,7 +4457,7 @@ instruct vsra16B_imm(vecX dst, vecX src, immI shift) %{
44574457
ins_pipe(vshift128_imm);
44584458
%}
44594459

4460-
instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
4460+
instruct vsrl8B_imm(vecD dst, vecD src, immI_positive shift) %{
44614461
predicate(n->as_Vector()->length() == 4 ||
44624462
n->as_Vector()->length() == 8);
44634463
match(Set dst (URShiftVB src (RShiftCntV shift)));
@@ -4477,7 +4477,7 @@ instruct vsrl8B_imm(vecD dst, vecD src, immI shift) %{
44774477
ins_pipe(vshift64_imm);
44784478
%}
44794479

4480-
instruct vsrl16B_imm(vecX dst, vecX src, immI shift) %{
4480+
instruct vsrl16B_imm(vecX dst, vecX src, immI_positive shift) %{
44814481
predicate(n->as_Vector()->length() == 16);
44824482
match(Set dst (URShiftVB src (RShiftCntV shift)));
44834483
ins_cost(INSN_COST);
@@ -4632,7 +4632,7 @@ instruct vsll8S_imm(vecX dst, vecX src, immI shift) %{
46324632
ins_pipe(vshift128_imm);
46334633
%}
46344634

4635-
instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
4635+
instruct vsra4S_imm(vecD dst, vecD src, immI_positive shift) %{
46364636
predicate(n->as_Vector()->length() == 2 ||
46374637
n->as_Vector()->length() == 4);
46384638
match(Set dst (RShiftVS src (RShiftCntV shift)));
@@ -4647,7 +4647,7 @@ instruct vsra4S_imm(vecD dst, vecD src, immI shift) %{
46474647
ins_pipe(vshift64_imm);
46484648
%}
46494649

4650-
instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
4650+
instruct vsra8S_imm(vecX dst, vecX src, immI_positive shift) %{
46514651
predicate(n->as_Vector()->length() == 8);
46524652
match(Set dst (RShiftVS src (RShiftCntV shift)));
46534653
ins_cost(INSN_COST);
@@ -4661,7 +4661,7 @@ instruct vsra8S_imm(vecX dst, vecX src, immI shift) %{
46614661
ins_pipe(vshift128_imm);
46624662
%}
46634663

4664-
instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
4664+
instruct vsrl4S_imm(vecD dst, vecD src, immI_positive shift) %{
46654665
predicate(n->as_Vector()->length() == 2 ||
46664666
n->as_Vector()->length() == 4);
46674667
match(Set dst (URShiftVS src (RShiftCntV shift)));
@@ -4681,7 +4681,7 @@ instruct vsrl4S_imm(vecD dst, vecD src, immI shift) %{
46814681
ins_pipe(vshift64_imm);
46824682
%}
46834683

4684-
instruct vsrl8S_imm(vecX dst, vecX src, immI shift) %{
4684+
instruct vsrl8S_imm(vecX dst, vecX src, immI_positive shift) %{
46854685
predicate(n->as_Vector()->length() == 8);
46864686
match(Set dst (URShiftVS src (RShiftCntV shift)));
46874687
ins_cost(INSN_COST);
@@ -4820,7 +4820,7 @@ instruct vsll4I_imm(vecX dst, vecX src, immI shift) %{
48204820
ins_pipe(vshift128_imm);
48214821
%}
48224822

4823-
instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
4823+
instruct vsra2I_imm(vecD dst, vecD src, immI_positive shift) %{
48244824
predicate(n->as_Vector()->length() == 2);
48254825
match(Set dst (RShiftVI src (RShiftCntV shift)));
48264826
ins_cost(INSN_COST);
@@ -4833,7 +4833,7 @@ instruct vsra2I_imm(vecD dst, vecD src, immI shift) %{
48334833
ins_pipe(vshift64_imm);
48344834
%}
48354835

4836-
instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
4836+
instruct vsra4I_imm(vecX dst, vecX src, immI_positive shift) %{
48374837
predicate(n->as_Vector()->length() == 4);
48384838
match(Set dst (RShiftVI src (RShiftCntV shift)));
48394839
ins_cost(INSN_COST);
@@ -4846,7 +4846,7 @@ instruct vsra4I_imm(vecX dst, vecX src, immI shift) %{
48464846
ins_pipe(vshift128_imm);
48474847
%}
48484848

4849-
instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
4849+
instruct vsrl2I_imm(vecD dst, vecD src, immI_positive shift) %{
48504850
predicate(n->as_Vector()->length() == 2);
48514851
match(Set dst (URShiftVI src (RShiftCntV shift)));
48524852
ins_cost(INSN_COST);
@@ -4859,7 +4859,7 @@ instruct vsrl2I_imm(vecD dst, vecD src, immI shift) %{
48594859
ins_pipe(vshift64_imm);
48604860
%}
48614861

4862-
instruct vsrl4I_imm(vecX dst, vecX src, immI shift) %{
4862+
instruct vsrl4I_imm(vecX dst, vecX src, immI_positive shift) %{
48634863
predicate(n->as_Vector()->length() == 4);
48644864
match(Set dst (URShiftVI src (RShiftCntV shift)));
48654865
ins_cost(INSN_COST);
@@ -4932,7 +4932,7 @@ instruct vsll2L_imm(vecX dst, vecX src, immI shift) %{
49324932
ins_pipe(vshift128_imm);
49334933
%}
49344934

4935-
instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
4935+
instruct vsra2L_imm(vecX dst, vecX src, immI_positive shift) %{
49364936
predicate(n->as_Vector()->length() == 2);
49374937
match(Set dst (RShiftVL src (RShiftCntV shift)));
49384938
ins_cost(INSN_COST);
@@ -4945,7 +4945,7 @@ instruct vsra2L_imm(vecX dst, vecX src, immI shift) %{
49454945
ins_pipe(vshift128_imm);
49464946
%}
49474947

4948-
instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
4948+
instruct vsrl2L_imm(vecX dst, vecX src, immI_positive shift) %{
49494949
predicate(n->as_Vector()->length() == 2);
49504950
match(Set dst (URShiftVL src (RShiftCntV shift)));
49514951
ins_cost(INSN_COST);
@@ -4958,7 +4958,7 @@ instruct vsrl2L_imm(vecX dst, vecX src, immI shift) %{
49584958
ins_pipe(vshift128_imm);
49594959
%}
49604960

4961-
instruct vsraa8B_imm(vecD dst, vecD src, immI shift) %{
4961+
instruct vsraa8B_imm(vecD dst, vecD src, immI_positive shift) %{
49624962
predicate(n->as_Vector()->length() == 8);
49634963
match(Set dst (AddVB dst (RShiftVB src (RShiftCntV shift))));
49644964
ins_cost(INSN_COST);
@@ -4972,7 +4972,7 @@ instruct vsraa8B_imm(vecD dst, vecD src, immI shift) %{
49724972
ins_pipe(vshift64_imm);
49734973
%}
49744974

4975-
instruct vsraa16B_imm(vecX dst, vecX src, immI shift) %{
4975+
instruct vsraa16B_imm(vecX dst, vecX src, immI_positive shift) %{
49764976
predicate(n->as_Vector()->length() == 16);
49774977
match(Set dst (AddVB dst (RShiftVB src (RShiftCntV shift))));
49784978
ins_cost(INSN_COST);
@@ -4986,7 +4986,7 @@ instruct vsraa16B_imm(vecX dst, vecX src, immI shift) %{
49864986
ins_pipe(vshift128_imm);
49874987
%}
49884988

4989-
instruct vsraa4S_imm(vecD dst, vecD src, immI shift) %{
4989+
instruct vsraa4S_imm(vecD dst, vecD src, immI_positive shift) %{
49904990
predicate(n->as_Vector()->length() == 4);
49914991
match(Set dst (AddVS dst (RShiftVS src (RShiftCntV shift))));
49924992
ins_cost(INSN_COST);
@@ -5000,7 +5000,7 @@ instruct vsraa4S_imm(vecD dst, vecD src, immI shift) %{
50005000
ins_pipe(vshift64_imm);
50015001
%}
50025002

5003-
instruct vsraa8S_imm(vecX dst, vecX src, immI shift) %{
5003+
instruct vsraa8S_imm(vecX dst, vecX src, immI_positive shift) %{
50045004
predicate(n->as_Vector()->length() == 8);
50055005
match(Set dst (AddVS dst (RShiftVS src (RShiftCntV shift))));
50065006
ins_cost(INSN_COST);
@@ -5014,7 +5014,7 @@ instruct vsraa8S_imm(vecX dst, vecX src, immI shift) %{
50145014
ins_pipe(vshift128_imm);
50155015
%}
50165016

5017-
instruct vsraa2I_imm(vecD dst, vecD src, immI shift) %{
5017+
instruct vsraa2I_imm(vecD dst, vecD src, immI_positive shift) %{
50185018
predicate(n->as_Vector()->length() == 2);
50195019
match(Set dst (AddVI dst (RShiftVI src (RShiftCntV shift))));
50205020
ins_cost(INSN_COST);
@@ -5027,7 +5027,7 @@ instruct vsraa2I_imm(vecD dst, vecD src, immI shift) %{
50275027
ins_pipe(vshift64_imm);
50285028
%}
50295029

5030-
instruct vsraa4I_imm(vecX dst, vecX src, immI shift) %{
5030+
instruct vsraa4I_imm(vecX dst, vecX src, immI_positive shift) %{
50315031
predicate(n->as_Vector()->length() == 4);
50325032
match(Set dst (AddVI dst (RShiftVI src (RShiftCntV shift))));
50335033
ins_cost(INSN_COST);
@@ -5040,7 +5040,7 @@ instruct vsraa4I_imm(vecX dst, vecX src, immI shift) %{
50405040
ins_pipe(vshift128_imm);
50415041
%}
50425042

5043-
instruct vsraa2L_imm(vecX dst, vecX src, immI shift) %{
5043+
instruct vsraa2L_imm(vecX dst, vecX src, immI_positive shift) %{
50445044
predicate(n->as_Vector()->length() == 2);
50455045
match(Set dst (AddVL dst (RShiftVL src (RShiftCntV shift))));
50465046
ins_cost(INSN_COST);
@@ -5053,7 +5053,7 @@ instruct vsraa2L_imm(vecX dst, vecX src, immI shift) %{
50535053
ins_pipe(vshift128_imm);
50545054
%}
50555055

5056-
instruct vsrla8B_imm(vecD dst, vecD src, immI shift) %{
5056+
instruct vsrla8B_imm(vecD dst, vecD src, immI_positive shift) %{
50575057
predicate(n->as_Vector()->length() == 8);
50585058
match(Set dst (AddVB dst (URShiftVB src (RShiftCntV shift))));
50595059
ins_cost(INSN_COST);
@@ -5068,7 +5068,7 @@ instruct vsrla8B_imm(vecD dst, vecD src, immI shift) %{
50685068
ins_pipe(vshift64_imm);
50695069
%}
50705070

5071-
instruct vsrla16B_imm(vecX dst, vecX src, immI shift) %{
5071+
instruct vsrla16B_imm(vecX dst, vecX src, immI_positive shift) %{
50725072
predicate(n->as_Vector()->length() == 16);
50735073
match(Set dst (AddVB dst (URShiftVB src (RShiftCntV shift))));
50745074
ins_cost(INSN_COST);
@@ -5083,7 +5083,7 @@ instruct vsrla16B_imm(vecX dst, vecX src, immI shift) %{
50835083
ins_pipe(vshift128_imm);
50845084
%}
50855085

5086-
instruct vsrla4S_imm(vecD dst, vecD src, immI shift) %{
5086+
instruct vsrla4S_imm(vecD dst, vecD src, immI_positive shift) %{
50875087
predicate(n->as_Vector()->length() == 4);
50885088
match(Set dst (AddVS dst (URShiftVS src (RShiftCntV shift))));
50895089
ins_cost(INSN_COST);
@@ -5098,7 +5098,7 @@ instruct vsrla4S_imm(vecD dst, vecD src, immI shift) %{
50985098
ins_pipe(vshift64_imm);
50995099
%}
51005100

5101-
instruct vsrla8S_imm(vecX dst, vecX src, immI shift) %{
5101+
instruct vsrla8S_imm(vecX dst, vecX src, immI_positive shift) %{
51025102
predicate(n->as_Vector()->length() == 8);
51035103
match(Set dst (AddVS dst (URShiftVS src (RShiftCntV shift))));
51045104
ins_cost(INSN_COST);
@@ -5113,7 +5113,7 @@ instruct vsrla8S_imm(vecX dst, vecX src, immI shift) %{
51135113
ins_pipe(vshift128_imm);
51145114
%}
51155115

5116-
instruct vsrla2I_imm(vecD dst, vecD src, immI shift) %{
5116+
instruct vsrla2I_imm(vecD dst, vecD src, immI_positive shift) %{
51175117
predicate(n->as_Vector()->length() == 2);
51185118
match(Set dst (AddVI dst (URShiftVI src (RShiftCntV shift))));
51195119
ins_cost(INSN_COST);
@@ -5126,7 +5126,7 @@ instruct vsrla2I_imm(vecD dst, vecD src, immI shift) %{
51265126
ins_pipe(vshift64_imm);
51275127
%}
51285128

5129-
instruct vsrla4I_imm(vecX dst, vecX src, immI shift) %{
5129+
instruct vsrla4I_imm(vecX dst, vecX src, immI_positive shift) %{
51305130
predicate(n->as_Vector()->length() == 4);
51315131
match(Set dst (AddVI dst (URShiftVI src (RShiftCntV shift))));
51325132
ins_cost(INSN_COST);
@@ -5139,7 +5139,7 @@ instruct vsrla4I_imm(vecX dst, vecX src, immI shift) %{
51395139
ins_pipe(vshift128_imm);
51405140
%}
51415141

5142-
instruct vsrla2L_imm(vecX dst, vecX src, immI shift) %{
5142+
instruct vsrla2L_imm(vecX dst, vecX src, immI_positive shift) %{
51435143
predicate(n->as_Vector()->length() == 2);
51445144
match(Set dst (AddVL dst (URShiftVL src (RShiftCntV shift))));
51455145
ins_cost(INSN_COST);

‎src/hotspot/cpu/aarch64/aarch64_neon_ad.m4

+4-4
Original file line numberDiff line numberDiff line change
@@ -1992,7 +1992,7 @@ instruct vsll$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
19921992
ins_pipe(vshift`'ifelse($6, D, 64, 128)_imm);
19931993
%}')dnl
19941994
define(`VSRA_IMM', `
1995-
instruct vsra$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
1995+
instruct vsra$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
19961996
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
19971997
',
19981998
$3$4, 4S, n->as_Vector()->length() == 2 ||`
@@ -2017,7 +2017,7 @@ instruct vsra$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
20172017
%}')dnl
20182018
dnl
20192019
define(`VSRL_IMM', `
2020-
instruct vsrl$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
2020+
instruct vsrl$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
20212021
predicate(ifelse($3$4, 8B, n->as_Vector()->length() == 4 ||`
20222022
',
20232023
$3$4, 4S, n->as_Vector()->length() == 2 ||`
@@ -2052,7 +2052,7 @@ instruct vsrl$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
20522052
%}')dnl
20532053
dnl
20542054
define(`VSRLA_IMM', `
2055-
instruct vsrla$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
2055+
instruct vsrla$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
20562056
predicate(n->as_Vector()->length() == $3);
20572057
match(Set dst (AddV$4 dst (URShiftV$4 src (RShiftCntV shift))));
20582058
ins_cost(INSN_COST);
@@ -2076,7 +2076,7 @@ instruct vsrla$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
20762076
%}')dnl
20772077
dnl
20782078
define(`VSRAA_IMM', `
2079-
instruct vsraa$3$4_imm`'(vec$6 dst, vec$6 src, immI shift) %{
2079+
instruct vsraa$3$4_imm`'(vec$6 dst, vec$6 src, immI_positive shift) %{
20802080
predicate(n->as_Vector()->length() == $3);
20812081
match(Set dst (AddV$4 dst (RShiftV$4 src (RShiftCntV shift))));
20822082
ins_cost(INSN_COST);
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,73 @@
1+
/*
2+
* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
3+
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4+
*
5+
* This code is free software; you can redistribute it and/or modify it
6+
* under the terms of the GNU General Public License version 2 only, as
7+
* published by the Free Software Foundation.
8+
*
9+
* This code is distributed in the hope that it will be useful, but WITHOUT
10+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12+
* version 2 for more details (a copy is included in the LICENSE file that
13+
* accompanied this code).
14+
*
15+
* You should have received a copy of the GNU General Public License version
16+
* 2 along with this work; if not, write to the Free Software Foundation,
17+
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18+
*
19+
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20+
* or visit www.oracle.com if you need additional information or have any
21+
* questions.
22+
*/
23+
24+
/*
25+
* @test
26+
* @bug 8288445
27+
* @summary Test shift by 0
28+
* @run main/othervm -Xbatch -XX:-TieredCompilation
29+
* compiler.codegen.ShiftByZero
30+
*/
31+
32+
package compiler.codegen;
33+
34+
public class ShiftByZero {
35+
36+
public static final int N = 64;
37+
38+
public static int[] i32 = new int[N];
39+
40+
public static void bMeth() {
41+
int shift = i32[0];
42+
// This loop is to confuse the optimizer, so that "shift" is
43+
// optimized to 0 only after loop vectorization.
44+
for (int i8 = 279; i8 > 1; --i8) {
45+
shift <<= 6;
46+
}
47+
// low 6 bits of shift are 0, so shift can be
48+
// simplified to constant 0
49+
{
50+
for (int i = 0; i < N; ++i) {
51+
i32[i] += i32[i] >>= shift;
52+
}
53+
for (int i = 0; i < N; ++i) {
54+
i32[i] += i32[i] >>>= shift;
55+
}
56+
for (int i = 0; i < N; ++i) {
57+
i32[i] >>>= shift;
58+
}
59+
for (int i = 0; i < N; ++i) {
60+
i32[i] >>= shift;
61+
}
62+
for (int i = 0; i < N; ++i) {
63+
i32[i] <<= shift;
64+
}
65+
}
66+
}
67+
68+
public static void main(String[] strArr) {
69+
for (int i = 0; i < 20_000; i++) {
70+
bMeth();
71+
}
72+
}
73+
}

3 commit comments

Comments
 (3)

openjdk-notifier[bot] commented on Sep 6, 2022

@openjdk-notifier[bot]

earthling-amzn commented on Oct 13, 2022

@earthling-amzn
Contributor

/backport jdk11u-dev

openjdk[bot] commented on Oct 13, 2022

@openjdk[bot]

@earthling-amzn Could not automatically backport 328ea9d0 to openjdk/jdk11u-dev due to conflicts in the following files:

  • src/hotspot/cpu/aarch64/aarch64_neon.ad
  • src/hotspot/cpu/aarch64/aarch64_neon_ad.m4

Please fetch the appropriate branch/commit and manually resolve these conflicts by using the following commands in your personal fork of openjdk/jdk11u-dev. Note: these commands are just some suggestions and you can use other equivalent commands you know.

# Fetch the up-to-date version of the target branch
$ git fetch --no-tags https://git.openjdk.org/jdk11u-dev master:master

# Check out the target branch and create your own branch to backport
$ git checkout master
$ git checkout -b earthling-amzn-backport-328ea9d0

# Fetch the commit you want to backport
$ git fetch --no-tags https://git.openjdk.org/jdk17u-dev 328ea9d0ff13a2b3f8c539589aa13178c2f50007

# Backport the commit
$ git cherry-pick --no-commit 328ea9d0ff13a2b3f8c539589aa13178c2f50007
# Resolve conflicts now

# Commit the files you have modified
$ git add files/with/resolved/conflicts
$ git commit -m 'Backport 328ea9d0ff13a2b3f8c539589aa13178c2f50007'

Once you have resolved the conflicts as explained above continue with creating a pull request towards the openjdk/jdk11u-dev with the title Backport 328ea9d0ff13a2b3f8c539589aa13178c2f50007.

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