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Commit 3283328

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author
Pengfei Li
committedJul 20, 2023
8311130: AArch64: Sync SVE related CPU features with VM options
Reviewed-by: aph, xgong
1 parent a742767 commit 3283328

10 files changed

+156
-51
lines changed
 

‎src/hotspot/cpu/aarch64/aarch64.ad

+1-1
Original file line numberDiff line numberDiff line change
@@ -2302,7 +2302,7 @@ bool Matcher::match_rule_supported(int opcode) {
23022302
break;
23032303
case Op_ExpandBits:
23042304
case Op_CompressBits:
2305-
if (!(UseSVE > 1 && VM_Version::supports_svebitperm())) {
2305+
if (!VM_Version::supports_svebitperm()) {
23062306
ret_value = false;
23072307
}
23082308
break;

‎src/hotspot/cpu/aarch64/aarch64_vector.ad

+2-2
Original file line numberDiff line numberDiff line change
@@ -216,13 +216,13 @@ source %{
216216
}
217217
break;
218218
case Op_VectorLongToMask:
219-
if (UseSVE < 2 || vlen > 64 || !VM_Version::supports_svebitperm()) {
219+
if (vlen > 64 || !VM_Version::supports_svebitperm()) {
220220
return false;
221221
}
222222
break;
223223
case Op_CompressBitsV:
224224
case Op_ExpandBitsV:
225-
if (UseSVE < 2 || !VM_Version::supports_svebitperm()) {
225+
if (!VM_Version::supports_svebitperm()) {
226226
return false;
227227
}
228228
break;

‎src/hotspot/cpu/aarch64/aarch64_vector_ad.m4

+2-2
Original file line numberDiff line numberDiff line change
@@ -206,13 +206,13 @@ source %{
206206
}
207207
break;
208208
case Op_VectorLongToMask:
209-
if (UseSVE < 2 || vlen > 64 || !VM_Version::supports_svebitperm()) {
209+
if (vlen > 64 || !VM_Version::supports_svebitperm()) {
210210
return false;
211211
}
212212
break;
213213
case Op_CompressBitsV:
214214
case Op_ExpandBitsV:
215-
if (UseSVE < 2 || !VM_Version::supports_svebitperm()) {
215+
if (!VM_Version::supports_svebitperm()) {
216216
return false;
217217
}
218218
break;

‎src/hotspot/cpu/aarch64/vm_version_aarch64.cpp

+36-23
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ void VM_Version::initialize() {
100100
PrefetchCopyIntervalInBytes = 32760;
101101
}
102102

103-
if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
103+
if (AllocatePrefetchDistance != -1 && (AllocatePrefetchDistance & 7)) {
104104
warning("AllocatePrefetchDistance must be multiple of 8");
105105
AllocatePrefetchDistance &= ~7;
106106
}
@@ -187,15 +187,15 @@ void VM_Version::initialize() {
187187
}
188188

189189
// Cortex A53
190-
if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
190+
if (_cpu == CPU_ARM && model_is(0xd03)) {
191191
_features |= CPU_A53MAC;
192192
if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
193193
FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
194194
}
195195
}
196196

197197
// Cortex A73
198-
if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
198+
if (_cpu == CPU_ARM && model_is(0xd09)) {
199199
if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
200200
FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
201201
}
@@ -206,9 +206,7 @@ void VM_Version::initialize() {
206206
}
207207

208208
// Neoverse N1, N2 and V1
209-
if (_cpu == CPU_ARM && ((_model == 0xd0c || _model2 == 0xd0c)
210-
|| (_model == 0xd49 || _model2 == 0xd49)
211-
|| (_model == 0xd40 || _model2 == 0xd40))) {
209+
if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) || model_is(0xd40))) {
212210
if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
213211
FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
214212
}
@@ -228,15 +226,6 @@ void VM_Version::initialize() {
228226
}
229227
}
230228

231-
char buf[512];
232-
int buf_used_len = os::snprintf_checked(buf, sizeof(buf), "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
233-
if (_model2) os::snprintf_checked(buf + buf_used_len, sizeof(buf) - buf_used_len, "(0x%03x)", _model2);
234-
#define ADD_FEATURE_IF_SUPPORTED(id, name, bit) if (VM_Version::supports_##name()) strcat(buf, ", " #name);
235-
CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
236-
#undef ADD_FEATURE_IF_SUPPORTED
237-
238-
_features_string = os::strdup(buf);
239-
240229
if (FLAG_IS_DEFAULT(UseCRC32)) {
241230
UseCRC32 = VM_Version::supports_crc32();
242231
}
@@ -247,7 +236,7 @@ void VM_Version::initialize() {
247236
}
248237

249238
// Neoverse V1
250-
if (_cpu == CPU_ARM && (_model == 0xd40 || _model2 == 0xd40)) {
239+
if (_cpu == CPU_ARM && model_is(0xd40)) {
251240
if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
252241
FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
253242
}
@@ -390,14 +379,14 @@ void VM_Version::initialize() {
390379
}
391380

392381
if (_features & CPU_ASIMD) {
393-
if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
394-
UseChaCha20Intrinsics = true;
395-
}
382+
if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
383+
UseChaCha20Intrinsics = true;
384+
}
396385
} else if (UseChaCha20Intrinsics) {
397-
if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
398-
warning("ChaCha20 intrinsic requires ASIMD instructions");
399-
}
400-
FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
386+
if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
387+
warning("ChaCha20 intrinsic requires ASIMD instructions");
388+
}
389+
FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
401390
}
402391

403392
if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
@@ -574,6 +563,30 @@ void VM_Version::initialize() {
574563
_spin_wait = get_spin_wait_desc();
575564

576565
check_virtualizations();
566+
567+
// Sync SVE related CPU features with flags
568+
if (UseSVE < 2) {
569+
_features &= ~CPU_SVE2;
570+
_features &= ~CPU_SVEBITPERM;
571+
}
572+
if (UseSVE < 1) {
573+
_features &= ~CPU_SVE;
574+
}
575+
576+
// Construct the "features" string
577+
char buf[512];
578+
int buf_used_len = os::snprintf_checked(buf, sizeof(buf), "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
579+
if (_model2) {
580+
os::snprintf_checked(buf + buf_used_len, sizeof(buf) - buf_used_len, "(0x%03x)", _model2);
581+
}
582+
#define ADD_FEATURE_IF_SUPPORTED(id, name, bit) \
583+
do { \
584+
if (VM_Version::supports_##name()) strcat(buf, ", " #name); \
585+
} while(0);
586+
CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
587+
#undef ADD_FEATURE_IF_SUPPORTED
588+
589+
_features_string = os::strdup(buf);
577590
}
578591

579592
#if defined(LINUX)

‎src/hotspot/cpu/aarch64/vm_version_aarch64.hpp

+4
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,10 @@ enum Ampere_CPU_Model {
151151
static int cpu_variant() { return _variant; }
152152
static int cpu_revision() { return _revision; }
153153

154+
static bool model_is(int cpu_model) {
155+
return _model == cpu_model || _model2 == cpu_model;
156+
}
157+
154158
static bool is_zva_enabled() { return 0 <= _zva_length; }
155159
static int zva_length() {
156160
assert(is_zva_enabled(), "ZVA not available");

‎test/hotspot/jtreg/compiler/arguments/TestSyncCPUFeaturesWithSVEFlags.java

+95
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
/*
2+
* Copyright (c) 2023, Arm Limited. All rights reserved.
3+
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4+
*
5+
* This code is free software; you can redistribute it and/or modify it
6+
* under the terms of the GNU General Public License version 2 only, as
7+
* published by the Free Software Foundation.
8+
*
9+
* This code is distributed in the hope that it will be useful, but WITHOUT
10+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12+
* version 2 for more details (a copy is included in the LICENSE file that
13+
* accompanied this code).
14+
*
15+
* You should have received a copy of the GNU General Public License version
16+
* 2 along with this work; if not, write to the Free Software Foundation,
17+
* Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18+
*
19+
* Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20+
* or visit www.oracle.com if you need additional information or have any
21+
* questions.
22+
*/
23+
24+
/*
25+
* @test
26+
* @bug 8311130
27+
* @summary Test synchronization between SVE arguments and CPU features
28+
*
29+
* @requires os.arch == "aarch64" & vm.compiler2.enabled
30+
* @library /test/lib /
31+
* @build jdk.test.whitebox.WhiteBox
32+
* @run driver jdk.test.lib.helpers.ClassFileInstaller
33+
* jdk.test.whitebox.WhiteBox
34+
*
35+
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
36+
* -XX:+WhiteBoxAPI -XX:UseSVE=0
37+
* compiler.arguments.TestSyncCPUFeaturesWithSVEFlags
38+
*
39+
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
40+
* -XX:+WhiteBoxAPI -XX:UseSVE=1
41+
* compiler.arguments.TestSyncCPUFeaturesWithSVEFlags
42+
*
43+
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
44+
* -XX:+WhiteBoxAPI -XX:UseSVE=2
45+
* compiler.arguments.TestSyncCPUFeaturesWithSVEFlags
46+
*
47+
* @run main/othervm -Xbootclasspath/a:. -XX:+UnlockDiagnosticVMOptions
48+
* -XX:+WhiteBoxAPI -XX:MaxVectorSize=8
49+
* compiler.arguments.TestSyncCPUFeaturesWithSVEFlags
50+
*/
51+
52+
package compiler.arguments;
53+
54+
import java.util.List;
55+
import java.util.Arrays;
56+
57+
import jdk.test.lib.Asserts;
58+
import jdk.test.whitebox.WhiteBox;
59+
60+
public class TestSyncCPUFeaturesWithSVEFlags {
61+
62+
private static final WhiteBox WB = WhiteBox.getWhiteBox();
63+
64+
public static void main(String[] args) {
65+
int sve_level = WB.getUintVMFlag("UseSVE").intValue();
66+
List<String> features = Arrays.asList(WB.getCPUFeatures().split(", "));
67+
boolean has_sve = features.contains("sve");
68+
boolean has_sve2 = features.contains("sve2");
69+
switch (sve_level) {
70+
case 0: {
71+
// No sve and sve2
72+
Asserts.assertFalse(has_sve);
73+
Asserts.assertFalse(has_sve2);
74+
break;
75+
}
76+
case 1: {
77+
// Only has sve, no sve2
78+
Asserts.assertTrue(has_sve);
79+
Asserts.assertFalse(has_sve2);
80+
break;
81+
}
82+
case 2: {
83+
// Has both sve and sve2
84+
Asserts.assertTrue(has_sve);
85+
Asserts.assertTrue(has_sve2);
86+
break;
87+
}
88+
default: {
89+
// Should not reach here
90+
Asserts.assertTrue(false);
91+
break;
92+
}
93+
}
94+
}
95+
}

‎test/hotspot/jtreg/compiler/intrinsics/TestBitShuffleOpers.java

+1-2
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,7 @@
3030
* @requires (((os.arch=="x86" | os.arch=="amd64" | os.arch=="x86_64") &
3131
* (vm.cpu.features ~= ".*bmi2.*" & vm.cpu.features ~= ".*bmi1.*" &
3232
* vm.cpu.features ~= ".*sse2.*")) |
33-
* ((vm.opt.UseSVE == "null" | vm.opt.UseSVE > 1) &
34-
* os.arch=="aarch64" & vm.cpu.features ~= ".*svebitperm.*"))
33+
* (os.arch=="aarch64" & vm.cpu.features ~= ".*svebitperm.*"))
3534
* @library /test/lib /
3635
* @run driver compiler.intrinsics.TestBitShuffleOpers
3736
*/

‎test/hotspot/jtreg/compiler/vectorapi/VectorLogicalOpIdentityTest.java

+11-17
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ public static void testMaskedAndMinusOne1() {
164164
@Test
165165
@Warmup(10000)
166166
@IR(counts = {IRNode.LOAD_VECTOR, ">=1"})
167-
@IR(failOn = IRNode.AND_V, applyIfCPUFeature = {"asimd", "true"}, applyIf = {"UseSVE", "0"})
167+
@IR(failOn = IRNode.AND_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
168168
public static void testMaskedAndMinusOne2() {
169169
VectorMask<Byte> mask = VectorMask.fromArray(B_SPECIES, m, 0);
170170
ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0);
@@ -185,7 +185,7 @@ public static void testMaskedAndMinusOne2() {
185185
@Test
186186
@Warmup(10000)
187187
@IR(counts = {IRNode.STORE_VECTOR, ">=1"})
188-
@IR(failOn = IRNode.AND_V, applyIfCPUFeature = {"asimd", "true"}, applyIf = {"UseSVE", "0"})
188+
@IR(failOn = IRNode.AND_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
189189
public static void testMaskedAndZero1() {
190190
VectorMask<Short> mask = VectorMask.fromArray(S_SPECIES, m, 0);
191191
ShortVector av = ShortVector.fromArray(S_SPECIES, sa, 0);
@@ -302,8 +302,7 @@ public static void testAndSameValue4() {
302302
// Transform AndV(AndV(a, b, m), b, m) ==> AndV(a, b, m)
303303
@Test
304304
@Warmup(10000)
305-
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeature = {"sve", "true"}, applyIf = {"UseSVE", "> 0"})
306-
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeature = {"avx512", "true"})
305+
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"})
307306
public static void testAndMaskSameValue1() {
308307
VectorMask<Integer> mask = VectorMask.fromArray(I_SPECIES, m, 0);
309308
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
@@ -324,8 +323,7 @@ public static void testAndMaskSameValue1() {
324323
// Transform AndV(AndV(a, b, m), a, m) ==> AndV(a, b, m)
325324
@Test
326325
@Warmup(10000)
327-
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeature = {"sve", "true"}, applyIf = {"UseSVE", "> 0"})
328-
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeature = {"avx512", "true"})
326+
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"})
329327
public static void testAndMaskSameValue2() {
330328
VectorMask<Long> mask = VectorMask.fromArray(L_SPECIES, m, 0);
331329
LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
@@ -346,8 +344,7 @@ public static void testAndMaskSameValue2() {
346344
// Transform AndV(a, AndV(a, b, m), m) ==> AndV(a, b, m)
347345
@Test
348346
@Warmup(10000)
349-
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeature = {"sve", "true"}, applyIf = {"UseSVE", "> 0"})
350-
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeature = {"avx512", "true"})
347+
@IR(counts = {IRNode.AND_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"})
351348
public static void testAndMaskSameValue3() {
352349
VectorMask<Integer> mask = VectorMask.fromArray(I_SPECIES, m, 0);
353350
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
@@ -412,7 +409,7 @@ public static void testOrSame() {
412409
@Test
413410
@Warmup(10000)
414411
@IR(counts = {IRNode.STORE_VECTOR, ">=1"})
415-
@IR(failOn = IRNode.OR_V, applyIfCPUFeature = {"asimd", "true"}, applyIf = {"UseSVE", "0"})
412+
@IR(failOn = IRNode.OR_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
416413
public static void testMaskedOrMinusOne1() {
417414
VectorMask<Byte> mask = VectorMask.fromArray(B_SPECIES, m, 0);
418415
ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0);
@@ -471,7 +468,7 @@ public static void testMaskedOrZero1() {
471468
@Test
472469
@Warmup(10000)
473470
@IR(counts = {IRNode.LOAD_VECTOR, ">=1"})
474-
@IR(failOn = IRNode.OR_V, applyIfCPUFeature = {"asimd", "true"}, applyIf = {"UseSVE", "0"})
471+
@IR(failOn = IRNode.OR_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
475472
public static void testMaskedOrZero2() {
476473
VectorMask<Byte> mask = VectorMask.fromArray(B_SPECIES, m, 0);
477474
ByteVector av = ByteVector.fromArray(B_SPECIES, ba, 0);
@@ -569,8 +566,7 @@ public static void testOrSameValue4() {
569566
// Transform OrV(OrV(a, b, m), b, m) ==> OrV(a, b, m)
570567
@Test
571568
@Warmup(10000)
572-
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeature = {"sve", "true"}, applyIf = {"UseSVE", "> 0"})
573-
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeature = {"avx512", "true"})
569+
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"})
574570
public static void testOrMaskSameValue1() {
575571
VectorMask<Integer> mask = VectorMask.fromArray(I_SPECIES, m, 0);
576572
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
@@ -591,8 +587,7 @@ public static void testOrMaskSameValue1() {
591587
// Transform OrV(OrV(a, b, m), a, m) ==> OrV(a, b, m)
592588
@Test
593589
@Warmup(10000)
594-
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeature = {"sve", "true"}, applyIf = {"UseSVE", "> 0"})
595-
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeature = {"avx512", "true"})
590+
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"})
596591
public static void testOrMaskSameValue2() {
597592
VectorMask<Long> mask = VectorMask.fromArray(L_SPECIES, m, 0);
598593
LongVector av = LongVector.fromArray(L_SPECIES, la, 0);
@@ -613,8 +608,7 @@ public static void testOrMaskSameValue2() {
613608
// Transform OrV(a, OrV(a, b, m), m) ==> OrV(a, b, m)
614609
@Test
615610
@Warmup(10000)
616-
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeature = {"sve", "true"}, applyIf = {"UseSVE", "> 0"})
617-
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeature = {"avx512", "true"})
611+
@IR(counts = {IRNode.OR_V, "1"}, applyIfCPUFeatureOr = {"sve", "true", "avx512", "true"})
618612
public static void testOrMaskSameValue3() {
619613
VectorMask<Integer> mask = VectorMask.fromArray(I_SPECIES, m, 0);
620614
IntVector av = IntVector.fromArray(I_SPECIES, ia, 0);
@@ -653,7 +647,7 @@ public static void testXorSame() {
653647
@Test
654648
@Warmup(10000)
655649
@IR(counts = {IRNode.STORE_VECTOR, ">=1"})
656-
@IR(failOn = IRNode.XOR_V, applyIfCPUFeature = {"asimd", "true"}, applyIf = {"UseSVE", "0"})
650+
@IR(failOn = IRNode.XOR_V, applyIfCPUFeatureAnd = {"asimd", "true", "sve", "false"})
657651
public static void testMaskedXorSame() {
658652
VectorMask<Short> mask = VectorMask.fromArray(S_SPECIES, m, 0);
659653
ShortVector av = ShortVector.fromArray(S_SPECIES, sa, 0);

‎test/hotspot/jtreg/compiler/vectorization/TestNumberOfContinuousZeros.java

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2022, Arm Limited. All rights reserved.
2+
* Copyright (c) 2022, 2023, Arm Limited. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
55
* This code is free software; you can redistribute it and/or modify it
@@ -27,7 +27,7 @@
2727
* @summary Test vectorization of numberOfTrailingZeros/numberOfLeadingZeros for Long
2828
* @requires vm.compiler2.enabled
2929
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") |
30-
* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*" & (vm.opt.UseSVE == "null" | vm.opt.UseSVE > 0))
30+
* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*")
3131
* @library /test/lib /
3232
* @run driver compiler.vectorization.TestNumberOfContinuousZeros
3333
*/

‎test/hotspot/jtreg/compiler/vectorization/TestPopulateIndex.java

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved.
2+
* Copyright (c) 2022, 2023, Oracle and/or its affiliates. All rights reserved.
33
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
44
*
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* This code is free software; you can redistribute it and/or modify it
@@ -27,7 +27,7 @@
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* @summary Test vectorization of loop induction variable usage in the loop
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* @requires vm.compiler2.enabled
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* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") |
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* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*" & (vm.opt.UseSVE == "null" | vm.opt.UseSVE > 0))
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* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*")
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* @library /test/lib /
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* @run driver compiler.vectorization.TestPopulateIndex
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*/

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