@@ -4478,34 +4478,15 @@ instruct loadD(regD dst, memory mem)
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ins_pipe(pipe_slow); // XXX
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%}
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-
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- // Following pseudo code describes the algorithm for max[FD]:
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- // Min algorithm is on similar lines
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- // btmp = (b < +0.0) ? a : b
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- // atmp = (b < +0.0) ? b : a
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- // Tmp = Max_Float(atmp , btmp)
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- // Res = (atmp == NaN) ? atmp : Tmp
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-
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// max = java.lang.Math.max(float a, float b)
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instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
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predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
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match(Set dst (MaxF a b));
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effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
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- format %{
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- "vblendvps $btmp,$b,$a,$b \n\t"
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- "vblendvps $atmp,$a,$b,$b \n\t"
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- "vmaxss $tmp,$atmp,$btmp \n\t"
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- "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
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- "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
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- %}
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- ins_encode %{
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- int vector_len = Assembler::AVX_128bit;
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- __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
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- __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
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- __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
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- __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
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- __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
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- %}
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+ format %{ "maxF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
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+ ins_encode %{
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+ __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
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+ %}
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ins_pipe( pipe_slow );
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%}
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@@ -4527,20 +4508,9 @@ instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp,
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predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
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match(Set dst (MaxD a b));
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effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
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- format %{
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- "vblendvpd $btmp,$b,$a,$b \n\t"
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- "vblendvpd $atmp,$a,$b,$b \n\t"
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- "vmaxsd $tmp,$atmp,$btmp \n\t"
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- "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
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- "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
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- %}
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+ format %{ "maxD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
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ins_encode %{
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- int vector_len = Assembler::AVX_128bit;
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- __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
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- __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
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- __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
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- __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
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- __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
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+ __ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
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%}
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ins_pipe( pipe_slow );
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%}
@@ -4563,20 +4533,9 @@ instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp,
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predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
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match(Set dst (MinF a b));
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effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
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- format %{
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- "vblendvps $atmp,$a,$b,$a \n\t"
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- "vblendvps $btmp,$b,$a,$a \n\t"
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- "vminss $tmp,$atmp,$btmp \n\t"
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- "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
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- "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
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- %}
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+ format %{ "minF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
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ins_encode %{
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- int vector_len = Assembler::AVX_128bit;
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- __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
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- __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
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- __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
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- __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
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- __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
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+ __ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
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%}
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ins_pipe( pipe_slow );
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%}
@@ -4599,20 +4558,9 @@ instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp,
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predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
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match(Set dst (MinD a b));
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effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
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- format %{
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- "vblendvpd $atmp,$a,$b,$a \n\t"
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- "vblendvpd $btmp,$b,$a,$a \n\t"
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- "vminsd $tmp,$atmp,$btmp \n\t"
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- "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
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- "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
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- %}
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- ins_encode %{
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- int vector_len = Assembler::AVX_128bit;
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- __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
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- __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
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- __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
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- __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
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- __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
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+ format %{ "minD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
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+ ins_encode %{
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+ __ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
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%}
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ins_pipe( pipe_slow );
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%}
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