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| 1 | +/* |
| 2 | + * Copyright (c) 2022, Oracle and/or its affiliates. All rights reserved. |
| 3 | + * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 4 | + * |
| 5 | + * This code is free software; you can redistribute it and/or modify it |
| 6 | + * under the terms of the GNU General Public License version 2 only, as |
| 7 | + * published by the Free Software Foundation. |
| 8 | + * |
| 9 | + * This code is distributed in the hope that it will be useful, but WITHOUT |
| 10 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 12 | + * version 2 for more details (a copy is included in the LICENSE file that |
| 13 | + * accompanied this code). |
| 14 | + * |
| 15 | + * You should have received a copy of the GNU General Public License version |
| 16 | + * 2 along with this work; if not, write to the Free Software Foundation, |
| 17 | + * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | + * |
| 19 | + * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA |
| 20 | + * or visit www.oracle.com if you need additional information or have any |
| 21 | + * questions. |
| 22 | + */ |
| 23 | +package jdk.vm.ci.riscv64; |
| 24 | + |
| 25 | +import java.nio.ByteOrder; |
| 26 | +import java.util.EnumSet; |
| 27 | + |
| 28 | +import jdk.vm.ci.code.Architecture; |
| 29 | +import jdk.vm.ci.code.CPUFeatureName; |
| 30 | +import jdk.vm.ci.code.Register; |
| 31 | +import jdk.vm.ci.code.Register.RegisterCategory; |
| 32 | +import jdk.vm.ci.code.RegisterArray; |
| 33 | +import jdk.vm.ci.meta.JavaKind; |
| 34 | +import jdk.vm.ci.meta.PlatformKind; |
| 35 | + |
| 36 | +/** |
| 37 | + * Represents the RISCV64 architecture. |
| 38 | + */ |
| 39 | +public class RISCV64 extends Architecture { |
| 40 | + |
| 41 | + public static final RegisterCategory CPU = new RegisterCategory("CPU"); |
| 42 | + |
| 43 | + // General purpose CPU registers |
| 44 | + public static final Register x0 = new Register(0, 0, "x0", CPU); |
| 45 | + public static final Register x1 = new Register(1, 1, "x1", CPU); |
| 46 | + public static final Register x2 = new Register(2, 2, "x2", CPU); |
| 47 | + public static final Register x3 = new Register(3, 3, "x3", CPU); |
| 48 | + public static final Register x4 = new Register(4, 4, "x4", CPU); |
| 49 | + public static final Register x5 = new Register(5, 5, "x5", CPU); |
| 50 | + public static final Register x6 = new Register(6, 6, "x6", CPU); |
| 51 | + public static final Register x7 = new Register(7, 7, "x7", CPU); |
| 52 | + public static final Register x8 = new Register(8, 8, "x8", CPU); |
| 53 | + public static final Register x9 = new Register(9, 9, "x9", CPU); |
| 54 | + public static final Register x10 = new Register(10, 10, "x10", CPU); |
| 55 | + public static final Register x11 = new Register(11, 11, "x11", CPU); |
| 56 | + public static final Register x12 = new Register(12, 12, "x12", CPU); |
| 57 | + public static final Register x13 = new Register(13, 13, "x13", CPU); |
| 58 | + public static final Register x14 = new Register(14, 14, "x14", CPU); |
| 59 | + public static final Register x15 = new Register(15, 15, "x15", CPU); |
| 60 | + public static final Register x16 = new Register(16, 16, "x16", CPU); |
| 61 | + public static final Register x17 = new Register(17, 17, "x17", CPU); |
| 62 | + public static final Register x18 = new Register(18, 18, "x18", CPU); |
| 63 | + public static final Register x19 = new Register(19, 19, "x19", CPU); |
| 64 | + public static final Register x20 = new Register(20, 20, "x20", CPU); |
| 65 | + public static final Register x21 = new Register(21, 21, "x21", CPU); |
| 66 | + public static final Register x22 = new Register(22, 22, "x22", CPU); |
| 67 | + public static final Register x23 = new Register(23, 23, "x23", CPU); |
| 68 | + public static final Register x24 = new Register(24, 24, "x24", CPU); |
| 69 | + public static final Register x25 = new Register(25, 25, "x25", CPU); |
| 70 | + public static final Register x26 = new Register(26, 26, "x26", CPU); |
| 71 | + public static final Register x27 = new Register(27, 27, "x27", CPU); |
| 72 | + public static final Register x28 = new Register(28, 28, "x28", CPU); |
| 73 | + public static final Register x29 = new Register(29, 29, "x29", CPU); |
| 74 | + public static final Register x30 = new Register(30, 30, "x30", CPU); |
| 75 | + public static final Register x31 = new Register(31, 31, "x31", CPU); |
| 76 | + |
| 77 | + // @formatter:off |
| 78 | + public static final RegisterArray cpuRegisters = new RegisterArray( |
| 79 | + x0, x1, x2, x3, x4, x5, x6, x7, |
| 80 | + x8, x9, x10, x11, x12, x13, x14, x15, |
| 81 | + x16, x17, x18, x19, x20, x21, x22, x23, |
| 82 | + x24, x25, x26, x27, x28, x29, x30, x31 |
| 83 | + ); |
| 84 | + // @formatter:on |
| 85 | + |
| 86 | + public static final RegisterCategory FP = new RegisterCategory("FP"); |
| 87 | + |
| 88 | + // Simd registers |
| 89 | + public static final Register f0 = new Register(32, 0, "f0", FP); |
| 90 | + public static final Register f1 = new Register(33, 1, "f1", FP); |
| 91 | + public static final Register f2 = new Register(34, 2, "f2", FP); |
| 92 | + public static final Register f3 = new Register(35, 3, "f3", FP); |
| 93 | + public static final Register f4 = new Register(36, 4, "f4", FP); |
| 94 | + public static final Register f5 = new Register(37, 5, "f5", FP); |
| 95 | + public static final Register f6 = new Register(38, 6, "f6", FP); |
| 96 | + public static final Register f7 = new Register(39, 7, "f7", FP); |
| 97 | + public static final Register f8 = new Register(40, 8, "f8", FP); |
| 98 | + public static final Register f9 = new Register(41, 9, "f9", FP); |
| 99 | + public static final Register f10 = new Register(42, 10, "f10", FP); |
| 100 | + public static final Register f11 = new Register(43, 11, "f11", FP); |
| 101 | + public static final Register f12 = new Register(44, 12, "f12", FP); |
| 102 | + public static final Register f13 = new Register(45, 13, "f13", FP); |
| 103 | + public static final Register f14 = new Register(46, 14, "f14", FP); |
| 104 | + public static final Register f15 = new Register(47, 15, "f15", FP); |
| 105 | + public static final Register f16 = new Register(48, 16, "f16", FP); |
| 106 | + public static final Register f17 = new Register(49, 17, "f17", FP); |
| 107 | + public static final Register f18 = new Register(50, 18, "f18", FP); |
| 108 | + public static final Register f19 = new Register(51, 19, "f19", FP); |
| 109 | + public static final Register f20 = new Register(52, 20, "f20", FP); |
| 110 | + public static final Register f21 = new Register(53, 21, "f21", FP); |
| 111 | + public static final Register f22 = new Register(54, 22, "f22", FP); |
| 112 | + public static final Register f23 = new Register(55, 23, "f23", FP); |
| 113 | + public static final Register f24 = new Register(56, 24, "f24", FP); |
| 114 | + public static final Register f25 = new Register(57, 25, "f25", FP); |
| 115 | + public static final Register f26 = new Register(58, 26, "f26", FP); |
| 116 | + public static final Register f27 = new Register(59, 27, "f27", FP); |
| 117 | + public static final Register f28 = new Register(60, 28, "f28", FP); |
| 118 | + public static final Register f29 = new Register(61, 29, "f29", FP); |
| 119 | + public static final Register f30 = new Register(62, 30, "f30", FP); |
| 120 | + public static final Register f31 = new Register(63, 31, "f31", FP); |
| 121 | + |
| 122 | + // @formatter:off |
| 123 | + public static final RegisterArray fpRegisters = new RegisterArray( |
| 124 | + f0, f1, f2, f3, f4, f5, f6, f7, |
| 125 | + f8, f9, f10, f11, f12, f13, f14, f15, |
| 126 | + f16, f17, f18, f19, f20, f21, f22, f23, |
| 127 | + f24, f25, f26, f27, f28, f29, f30, f31 |
| 128 | + ); |
| 129 | + // @formatter:on |
| 130 | + |
| 131 | + // @formatter:off |
| 132 | + public static final RegisterArray allRegisters = new RegisterArray( |
| 133 | + x0, x1, x2, x3, x4, x5, x6, x7, |
| 134 | + x8, x9, x10, x11, x12, x13, x14, x15, |
| 135 | + x16, x17, x18, x19, x20, x21, x22, x23, |
| 136 | + x24, x25, x26, x27, x28, x29, x30, x31, |
| 137 | + |
| 138 | + f0, f1, f2, f3, f4, f5, f6, f7, |
| 139 | + f8, f9, f10, f11, f12, f13, f14, f15, |
| 140 | + f16, f17, f18, f19, f20, f21, f22, f23, |
| 141 | + f24, f25, f26, f27, f28, f29, f30, f31 |
| 142 | + ); |
| 143 | + // @formatter:on |
| 144 | + |
| 145 | + /** |
| 146 | + * Basic set of CPU features mirroring what is returned from the mcpuid register. See: |
| 147 | + * {@code VM_Version::cpuFeatureFlags}. |
| 148 | + */ |
| 149 | + public enum CPUFeature implements CPUFeatureName { |
| 150 | + I, |
| 151 | + M, |
| 152 | + A, |
| 153 | + F, |
| 154 | + D, |
| 155 | + C, |
| 156 | + V |
| 157 | + } |
| 158 | + |
| 159 | + private final EnumSet<CPUFeature> features; |
| 160 | + |
| 161 | + /** |
| 162 | + * Set of flags to control code emission. |
| 163 | + */ |
| 164 | + public enum Flag { |
| 165 | + UseConservativeFence, |
| 166 | + AvoidUnalignedAccesses, |
| 167 | + NearCpool, |
| 168 | + TraceTraps, |
| 169 | + UseRVV, |
| 170 | + UseRVC, |
| 171 | + UseZba, |
| 172 | + UseZbb, |
| 173 | + UseRVVForBigIntegerShiftIntrinsics |
| 174 | + } |
| 175 | + |
| 176 | + private final EnumSet<Flag> flags; |
| 177 | + |
| 178 | + public RISCV64(EnumSet<CPUFeature> features, EnumSet<Flag> flags) { |
| 179 | + super("riscv64", RISCV64Kind.QWORD, ByteOrder.LITTLE_ENDIAN, true, allRegisters, 0, 0, 8); |
| 180 | + this.features = features; |
| 181 | + this.flags = flags; |
| 182 | + } |
| 183 | + |
| 184 | + @Override |
| 185 | + public EnumSet<CPUFeature> getFeatures() { |
| 186 | + return features; |
| 187 | + } |
| 188 | + |
| 189 | + public EnumSet<Flag> getFlags() { |
| 190 | + return flags; |
| 191 | + } |
| 192 | + |
| 193 | + @Override |
| 194 | + public PlatformKind getPlatformKind(JavaKind javaKind) { |
| 195 | + switch (javaKind) { |
| 196 | + case Boolean: |
| 197 | + case Byte: |
| 198 | + return RISCV64Kind.BYTE; |
| 199 | + case Short: |
| 200 | + case Char: |
| 201 | + return RISCV64Kind.WORD; |
| 202 | + case Int: |
| 203 | + return RISCV64Kind.DWORD; |
| 204 | + case Long: |
| 205 | + case Object: |
| 206 | + return RISCV64Kind.QWORD; |
| 207 | + case Float: |
| 208 | + return RISCV64Kind.SINGLE; |
| 209 | + case Double: |
| 210 | + return RISCV64Kind.DOUBLE; |
| 211 | + default: |
| 212 | + return null; |
| 213 | + } |
| 214 | + } |
| 215 | + |
| 216 | + @Override |
| 217 | + public boolean canStoreValue(RegisterCategory category, PlatformKind platformKind) { |
| 218 | + RISCV64Kind kind = (RISCV64Kind) platformKind; |
| 219 | + if (kind.isInteger()) { |
| 220 | + return category.equals(CPU); |
| 221 | + } else if (kind.isFP()) { |
| 222 | + return category.equals(FP); |
| 223 | + } |
| 224 | + return false; |
| 225 | + } |
| 226 | + |
| 227 | + @Override |
| 228 | + public RISCV64Kind getLargestStorableKind(RegisterCategory category) { |
| 229 | + if (category.equals(CPU)) { |
| 230 | + return RISCV64Kind.QWORD; |
| 231 | + } else if (category.equals(FP)) { |
| 232 | + return RISCV64Kind.DOUBLE; |
| 233 | + } else { |
| 234 | + return null; |
| 235 | + } |
| 236 | + } |
| 237 | +} |
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