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TheRealMDoerrTheRealMDoerr
committedNov 24, 2022
8297445: PPC64: Represent Registers as values
Reviewed-by: mbaesken, rrich
1 parent 2f8a5c2 commit 9c77e41

13 files changed

+395
-661
lines changed
 

‎src/hotspot/cpu/ppc/assembler_ppc.hpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2002, 2022, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
3+
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -1932,7 +1932,7 @@ class Assembler : public AbstractAssembler {
19321932

19331933
// More convenient version.
19341934
int condition_register_bit(ConditionRegister cr, Condition c) {
1935-
return 4 * (int)(intptr_t)cr + c;
1935+
return 4 * cr.encoding() + c;
19361936
}
19371937
void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);
19381938
void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc);

‎src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
3+
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -577,7 +577,7 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
577577
case Bytecodes::_f2i: {
578578
bool dst_in_memory = !VM_Version::has_mtfprd();
579579
FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
580-
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
580+
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
581581
Label L;
582582
// Result must be 0 if value is NaN; test by comparing value to itself.
583583
__ fcmpu(CCR0, rsrc, rsrc);
@@ -601,7 +601,7 @@ void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
601601
case Bytecodes::_f2l: {
602602
bool dst_in_memory = !VM_Version::has_mtfprd();
603603
FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
604-
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
604+
Address addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : Address();
605605
Label L;
606606
// Result must be 0 if value is NaN; test by comparing value to itself.
607607
__ fcmpu(CCR0, rsrc, rsrc);

‎src/hotspot/cpu/ppc/gc/z/zBarrierSetAssembler_ppc.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -540,15 +540,15 @@ class ZSetupArguments {
540540

541541
if (_ref != R4_ARG2) {
542542
// Calculate address first as the address' base register might clash with R4_ARG2
543-
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base());
543+
__ addi(R4_ARG2, _ref_addr.base(), _ref_addr.disp());
544544
__ mr_if_needed(R3_ARG1, _ref);
545545
} else if (_ref_addr.base() != R3_ARG1) {
546546
__ mr(R3_ARG1, _ref);
547-
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base()); // Clobbering _ref
547+
__ addi(R4_ARG2, _ref_addr.base(), _ref_addr.disp()); // Clobbering _ref
548548
} else {
549549
// Arguments are provided in inverse order (i.e. _ref == R4_ARG2, _ref_addr == R3_ARG1)
550550
__ mr(R0, _ref);
551-
__ add(R4_ARG2, (intptr_t) _ref_addr.disp(), _ref_addr.base());
551+
__ addi(R4_ARG2, _ref_addr.base(), _ref_addr.disp());
552552
__ mr(R3_ARG1, R0);
553553
}
554554
}

‎src/hotspot/cpu/ppc/interp_masm_ppc_64.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 2003, 2022, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
3+
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -1769,7 +1769,7 @@ void InterpreterMacroAssembler::profile_arguments_type(Register callee,
17691769
if (MethodData::profile_arguments()) {
17701770
Label done;
17711771
int off_to_args = in_bytes(TypeEntriesAtCall::args_data_offset());
1772-
add(R28_mdx, off_to_args, R28_mdx);
1772+
addi(R28_mdx, R28_mdx, off_to_args);
17731773

17741774
for (int i = 0; i < TypeProfileArgsLimit; i++) {
17751775
if (i > 0 || MethodData::profile_return()) {

‎src/hotspot/cpu/ppc/methodHandles_ppc.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2012, 2021 SAP SE. All rights reserved.
3+
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -301,7 +301,7 @@ address MethodHandles::generate_method_handle_interpreter_entry(MacroAssembler*
301301
}
302302
Register R19_member = R19_method; // MemberName ptr; incoming method ptr is dead now
303303
__ ld(R19_member, RegisterOrConstant((intptr_t)8), R15_argbase);
304-
__ add(R15_argbase, Interpreter::stackElementSize, R15_argbase);
304+
__ addi(R15_argbase, R15_argbase, Interpreter::stackElementSize);
305305
generate_method_handle_dispatch(_masm, iid, tmp_recv, R19_member, not_for_compiler_entry);
306306
}
307307

‎src/hotspot/cpu/ppc/register_ppc.cpp

+14-15
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
2-
* Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
3-
* Copyright (c) 2012, 2018 SAP SE. All rights reserved.
2+
* Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
3+
* Copyright (c) 2012, 2022 SAP SE. All rights reserved.
44
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
55
*
66
* This code is free software; you can redistribute it and/or modify it
@@ -26,8 +26,7 @@
2626
#include "precompiled.hpp"
2727
#include "register_ppc.hpp"
2828

29-
30-
const char* RegisterImpl::name() const {
29+
const char* Register::name() const {
3130
const char* names[number_of_registers] = {
3231
"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
3332
"R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15",
@@ -37,14 +36,14 @@ const char* RegisterImpl::name() const {
3736
return is_valid() ? names[encoding()] : "noreg";
3837
}
3938

40-
const char* ConditionRegisterImpl::name() const {
39+
const char* ConditionRegister::name() const {
4140
const char* names[number_of_registers] = {
4241
"CR0", "CR1", "CR2", "CR3", "CR4", "CR5", "CR6", "CR7"
4342
};
4443
return is_valid() ? names[encoding()] : "cnoreg";
4544
}
4645

47-
const char* FloatRegisterImpl::name() const {
46+
const char* FloatRegister::name() const {
4847
const char* names[number_of_registers] = {
4948
"F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7",
5049
"F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15",
@@ -54,14 +53,14 @@ const char* FloatRegisterImpl::name() const {
5453
return is_valid() ? names[encoding()] : "fnoreg";
5554
}
5655

57-
const char* SpecialRegisterImpl::name() const {
56+
const char* SpecialRegister::name() const {
5857
const char* names[number_of_registers] = {
5958
"SR_XER", "SR_LR", "SR_CTR", "SR_VRSAVE", "SR_SPEFSCR", "SR_PPR"
6059
};
6160
return is_valid() ? names[encoding()] : "snoreg";
6261
}
6362

64-
const char* VectorRegisterImpl::name() const {
63+
const char* VectorRegister::name() const {
6564
const char* names[number_of_registers] = {
6665
"VR0", "VR1", "VR2", "VR3", "VR4", "VR5", "VR6", "VR7",
6766
"VR8", "VR9", "VR10", "VR11", "VR12", "VR13", "VR14", "VR15",
@@ -71,7 +70,7 @@ const char* VectorRegisterImpl::name() const {
7170
return is_valid() ? names[encoding()] : "vnoreg";
7271
}
7372

74-
const char* VectorSRegisterImpl::name() const {
73+
const char* VectorSRegister::name() const {
7574
const char* names[number_of_registers] = {
7675
"VSR0", "VSR1", "VSR2", "VSR3", "VSR4", "VSR5", "VSR6", "VSR7",
7776
"VSR8", "VSR9", "VSR10", "VSR11", "VSR12", "VSR13", "VSR14", "VSR15",
@@ -86,19 +85,19 @@ const char* VectorSRegisterImpl::name() const {
8685
}
8786

8887
// Method to convert a FloatRegister to a Vector-Scalar Register (VectorSRegister)
89-
VectorSRegister FloatRegisterImpl::to_vsr() const {
90-
if (this == fnoreg) { return vsnoreg; }
88+
VectorSRegister FloatRegister::to_vsr() const {
89+
if (*this == fnoreg) { return vsnoreg; }
9190
return as_VectorSRegister(encoding());
9291
}
9392

9493
// Method to convert a VectorRegister to a Vector-Scalar Register (VectorSRegister)
95-
VectorSRegister VectorRegisterImpl::to_vsr() const {
96-
if (this == vnoreg) { return vsnoreg; }
94+
VectorSRegister VectorRegister::to_vsr() const {
95+
if (*this == vnoreg) { return vsnoreg; }
9796
return as_VectorSRegister(encoding() + 32);
9897
}
9998

10099
// Method to convert a VectorSRegister to a Vector Register (VectorRegister)
101-
VectorRegister VectorSRegisterImpl::to_vr() const {
102-
if (this == vsnoreg) { return vnoreg; }
100+
VectorRegister VectorSRegister::to_vr() const {
101+
if (*this == vsnoreg) { return vnoreg; }
103102
return as_VectorRegister(encoding() - 32);
104103
}

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