diff --git a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
index 63f193de86e..fdd2c0ca3d7 100644
--- a/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
+++ b/src/hotspot/cpu/aarch64/c1_LIRAssembler_aarch64.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2020, Oracle and/or its affiliates. All rights reserved.
* Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
@@ -1593,9 +1593,7 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
}
-void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
- LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
- assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on aarch64");
+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
Assembler::Condition acond, ncond;
switch (condition) {
diff --git a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
index cb095052534..f0a7229aa18 100644
--- a/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
+++ b/src/hotspot/cpu/arm/c1_LIRAssembler_arm.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2008, 2022, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -1824,10 +1824,7 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
}
-void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
- LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
- assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on arm");
-
+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
AsmCondition acond = al;
AsmCondition ncond = nv;
if (opr1 != opr2) {
diff --git a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
index 009fc44a6b9..f563d83f60b 100644
--- a/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
+++ b/src/hotspot/cpu/ppc/c1_LIRAssembler_ppc.cpp
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
+ * Copyright (c) 2000, 2019, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2012, 2019, SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -1553,10 +1553,7 @@ inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
}
}
-void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
- LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
- assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on ppc");
-
+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
load_to_reg(this, opr1, result); // Condition doesn't matter.
return;
diff --git a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
index ee298f56653..897be2209e2 100644
--- a/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
+++ b/src/hotspot/cpu/s390/c1_LIRAssembler_s390.cpp
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2016, 2022, Oracle and/or its affiliates. All rights reserved.
- * Copyright (c) 2016, 2019 SAP SE. All rights reserved.
+ * Copyright (c) 2016, 2019, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2016, 2019, SAP SE. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -1447,10 +1447,7 @@ void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Op
}
// result = condition ? opr1 : opr2
-void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
- LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
- assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on s390");
-
+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
Assembler::branch_condition acond = Assembler::bcondEqual, ncond = Assembler::bcondNotEqual;
switch (condition) {
case lir_cond_equal: acond = Assembler::bcondEqual; ncond = Assembler::bcondNotEqual; break;
diff --git a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
index 82e9de5a06f..cee3140f4f7 100644
--- a/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
+++ b/src/hotspot/cpu/x86/c1_LIRAssembler_x86.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2000, 2022, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it
@@ -1970,10 +1970,7 @@ void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
}
}
-void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type,
- LIR_Opr cmp_opr1, LIR_Opr cmp_opr2) {
- assert(cmp_opr1 == LIR_OprFact::illegalOpr && cmp_opr2 == LIR_OprFact::illegalOpr, "unnecessary cmp oprs on x86");
-
+void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
Assembler::Condition acond, ncond;
switch (condition) {
case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break;
diff --git a/src/hotspot/share/c1/c1_LIR.cpp b/src/hotspot/share/c1/c1_LIR.cpp
index 733ee9e654c..c640c546b1d 100644
--- a/src/hotspot/share/c1/c1_LIR.cpp
+++ b/src/hotspot/share/c1/c1_LIR.cpp
@@ -199,6 +199,10 @@ bool LIR_OprDesc::is_oop() const {
void LIR_Op2::verify() const {
#ifdef ASSERT
switch (code()) {
+ case lir_cmove:
+#ifdef RISCV
+ assert(false, "lir_cmove is LIR_Op4 on RISCV");
+#endif
case lir_xchg:
break;
@@ -251,7 +255,13 @@ void LIR_Op2::verify() const {
LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
+#ifdef RISCV
: LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL, type)
+#else
+ : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
+ , _cond(cond)
+ , _type(type)
+#endif
, _label(block->label())
, _block(block)
, _ublock(NULL)
@@ -259,7 +269,13 @@ LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block
}
LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
+#ifdef RISCV
LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL, type)
+#else
+ LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
+ , _cond(cond)
+ , _type(type)
+#endif
, _label(stub->entry())
, _block(NULL)
, _ublock(NULL)
@@ -267,7 +283,13 @@ LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
}
LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
+#ifdef RISCV
: LIR_Op2(lir_cond_float_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL, type)
+#else
+ : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
+ , _cond(cond)
+ , _type(type)
+#endif
, _label(block->label())
, _block(block)
, _ublock(ublock)
@@ -518,12 +540,14 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
assert(op->as_OpBranch() != NULL, "must be");
LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
+#ifdef RISCV
assert(opBranch->_tmp1->is_illegal() && opBranch->_tmp2->is_illegal() &&
opBranch->_tmp3->is_illegal() && opBranch->_tmp4->is_illegal() &&
opBranch->_tmp5->is_illegal(), "not used");
if (opBranch->_opr1->is_valid()) do_input(opBranch->_opr1);
if (opBranch->_opr2->is_valid()) do_input(opBranch->_opr2);
+#endif
if (opBranch->_info != NULL) do_info(opBranch->_info);
assert(opBranch->_result->is_illegal(), "not used");
@@ -615,6 +639,7 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
// to the result operand, otherwise the backend fails
case lir_cmove:
{
+#ifdef RISCV
assert(op->as_Op4() != NULL, "must be");
LIR_Op4* op4 = (LIR_Op4*)op;
@@ -628,6 +653,19 @@ void LIR_OpVisitState::visit(LIR_Op* op) {
if (op4->_opr4->is_valid()) do_input(op4->_opr4);
do_temp(op4->_opr2);
do_output(op4->_result);
+#else
+ assert(op->as_Op2() != NULL, "must be");
+ LIR_Op2* op2 = (LIR_Op2*)op;
+
+ assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
+ op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
+ assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
+
+ do_input(op2->_opr1);
+ do_input(op2->_opr2);
+ do_temp(op2->_opr2);
+ do_output(op2->_result);
+#endif
break;
}
@@ -1050,9 +1088,11 @@ void LIR_Op3::emit_code(LIR_Assembler* masm) {
masm->emit_op3(this);
}
+#ifdef RISCV
void LIR_Op4::emit_code(LIR_Assembler* masm) {
masm->emit_op4(this);
}
+#endif
void LIR_OpLock::emit_code(LIR_Assembler* masm) {
masm->emit_lock(this);
@@ -1722,6 +1762,7 @@ const char * LIR_Op::name() const {
case lir_cmp_l2i: s = "cmp_l2i"; break;
case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
case lir_cmp_fd2i: s = "comp_fd2i"; break;
+ case lir_cmove: s = "cmove"; break;
case lir_add: s = "add"; break;
case lir_sub: s = "sub"; break;
case lir_mul: s = "mul"; break;
@@ -1746,8 +1787,6 @@ const char * LIR_Op::name() const {
case lir_irem: s = "irem"; break;
case lir_fmad: s = "fmad"; break;
case lir_fmaf: s = "fmaf"; break;
- // LIR_Op4
- case lir_cmove: s = "cmove"; break;
// LIR_OpJavaCall
case lir_static_call: s = "static"; break;
case lir_optvirtual_call: s = "optvirtual"; break;
@@ -1884,8 +1923,10 @@ void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
// LIR_OpBranch
void LIR_OpBranch::print_instr(outputStream* out) const {
print_condition(out, cond()); out->print(" ");
+#ifdef RISCV
in_opr1()->print(out); out->print(" ");
in_opr2()->print(out); out->print(" ");
+#endif
if (block() != NULL) {
out->print("[B%d] ", block()->block_id());
} else if (stub() != NULL) {
@@ -1972,7 +2013,11 @@ void LIR_OpRoundFP::print_instr(outputStream* out) const {
// LIR_Op2
void LIR_Op2::print_instr(outputStream* out) const {
+#ifdef RISCV
if (code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch) {
+#else
+ if (code() == lir_cmove || code() == lir_cmp) {
+#endif
print_condition(out, condition()); out->print(" ");
}
in_opr1()->print(out); out->print(" ");
@@ -2023,6 +2068,7 @@ void LIR_Op3::print_instr(outputStream* out) const {
result_opr()->print(out);
}
+#ifdef RISCV
// LIR_Op4
void LIR_Op4::print_instr(outputStream* out) const {
print_condition(out, condition()); out->print(" ");
@@ -2032,6 +2078,7 @@ void LIR_Op4::print_instr(outputStream* out) const {
in_opr4()->print(out); out->print(" ");
result_opr()->print(out);
}
+#endif
void LIR_OpLock::print_instr(outputStream* out) const {
hdr_opr()->print(out); out->print(" ");
diff --git a/src/hotspot/share/c1/c1_LIR.hpp b/src/hotspot/share/c1/c1_LIR.hpp
index efff6bf7a30..33943e369da 100644
--- a/src/hotspot/share/c1/c1_LIR.hpp
+++ b/src/hotspot/share/c1/c1_LIR.hpp
@@ -867,7 +867,9 @@ class LIR_Op2;
class LIR_OpDelay;
class LIR_Op3;
class LIR_OpAllocArray;
+#ifdef RISCV
class LIR_Op4;
+#endif
class LIR_OpCall;
class LIR_OpJavaCall;
class LIR_OpRTCall;
@@ -917,6 +919,10 @@ enum LIR_Code {
, lir_null_check
, lir_return
, lir_leal
+#ifndef RISCV
+ , lir_branch
+ , lir_cond_float_branch
+#endif
, lir_move
, lir_convert
, lir_alloc_object
@@ -928,12 +934,17 @@ enum LIR_Code {
, lir_unwind
, end_op1
, begin_op2
+#ifdef RISCV
, lir_branch
, lir_cond_float_branch
+#endif
, lir_cmp
, lir_cmp_l2i
, lir_ucmp_fd2i
, lir_cmp_fd2i
+#ifndef RISCV
+ , lir_cmove
+#endif
, lir_add
, lir_sub
, lir_mul
@@ -964,9 +975,11 @@ enum LIR_Code {
, lir_fmad
, lir_fmaf
, end_op3
+#ifdef RISCV
, begin_op4
, lir_cmove
, end_op4
+#endif
, begin_opJavaCall
, lir_static_call
, lir_optvirtual_call
@@ -1004,7 +1017,7 @@ enum LIR_Code {
, begin_opAssert
, lir_assert
, end_opAssert
-#ifdef INCLUDE_ZGC
+#if defined(RISCV) && defined(INCLUDE_ZGC)
, begin_opZLoadBarrierTest
, lir_zloadbarrier_test
, end_opZLoadBarrierTest
@@ -1142,7 +1155,9 @@ class LIR_Op: public CompilationResourceObj {
virtual LIR_Op1* as_Op1() { return NULL; }
virtual LIR_Op2* as_Op2() { return NULL; }
virtual LIR_Op3* as_Op3() { return NULL; }
+#ifdef RISCV
virtual LIR_Op4* as_Op4() { return NULL; }
+#endif
virtual LIR_OpArrayCopy* as_OpArrayCopy() { return NULL; }
virtual LIR_OpUpdateCRC32* as_OpUpdateCRC32() { return NULL; }
virtual LIR_OpTypeCheck* as_OpTypeCheck() { return NULL; }
@@ -1590,7 +1605,7 @@ class LIR_Op2: public LIR_Op {
, _tmp4(LIR_OprFact::illegalOpr)
, _tmp5(LIR_OprFact::illegalOpr)
, _condition(condition) {
- assert(code == lir_cmp || code == lir_branch || code == lir_cond_float_branch || code == lir_assert, "code check");
+ assert(code == lir_cmp || code == lir_assert RISCV_ONLY(|| code == lir_branch || code == lir_cond_float_branch), "code check");
}
LIR_Op2(LIR_Code code, LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type)
@@ -1622,7 +1637,7 @@ class LIR_Op2: public LIR_Op {
, _tmp4(LIR_OprFact::illegalOpr)
, _tmp5(LIR_OprFact::illegalOpr)
, _condition(lir_cond_unknown) {
- assert(code != lir_cmp && code != lir_branch && code != lir_cond_float_branch && is_in_range(code, begin_op2, end_op2), "code check");
+ assert(code != lir_cmp && RISCV_ONLY(code != lir_branch && code != lir_cond_float_branch &&) is_in_range(code, begin_op2, end_op2), "code check");
}
LIR_Op2(LIR_Code code, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, LIR_Opr tmp1, LIR_Opr tmp2 = LIR_OprFact::illegalOpr,
@@ -1638,7 +1653,7 @@ class LIR_Op2: public LIR_Op {
, _tmp4(tmp4)
, _tmp5(tmp5)
, _condition(lir_cond_unknown) {
- assert(code != lir_cmp && code != lir_branch && code != lir_cond_float_branch && is_in_range(code, begin_op2, end_op2), "code check");
+ assert(code != lir_cmp && RISCV_ONLY(code != lir_branch && code != lir_cond_float_branch &&) is_in_range(code, begin_op2, end_op2), "code check");
}
LIR_Opr in_opr1() const { return _opr1; }
@@ -1650,10 +1665,18 @@ class LIR_Op2: public LIR_Op {
LIR_Opr tmp4_opr() const { return _tmp4; }
LIR_Opr tmp5_opr() const { return _tmp5; }
LIR_Condition condition() const {
+#ifdef RISCV
assert(code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch || code() == lir_assert, "only valid for branch and assert"); return _condition;
+#else
+ assert(code() == lir_cmp || code() == lir_cmove || code() == lir_assert, "only valid for cmp and cmove and assert"); return _condition;
+#endif
}
void set_condition(LIR_Condition condition) {
+#ifdef RISCV
assert(code() == lir_cmp || code() == lir_branch || code() == lir_cond_float_branch, "only valid for branch"); _condition = condition;
+#else
+ assert(code() == lir_cmp || code() == lir_cmove, "only valid for cmp and cmove"); _condition = condition;
+#endif
}
void set_fpu_stack_size(int size) { _fpu_stack_size = size; }
@@ -1667,10 +1690,18 @@ class LIR_Op2: public LIR_Op {
virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
};
+#ifdef RISCV
class LIR_OpBranch: public LIR_Op2 {
+#else
+class LIR_OpBranch: public LIR_Op {
+#endif
friend class LIR_OpVisitState;
private:
+#ifndef RISCV
+ LIR_Condition _cond;
+ BasicType _type;
+#endif
Label* _label;
BlockBegin* _block; // if this is a branch to a block, this is the block
BlockBegin* _ublock; // if this is a float-branch, this is the unorderd block
@@ -1678,7 +1709,13 @@ class LIR_OpBranch: public LIR_Op2 {
public:
LIR_OpBranch(LIR_Condition cond, BasicType type, Label* lbl)
+#ifdef RISCV
: LIR_Op2(lir_branch, cond, LIR_OprFact::illegalOpr, LIR_OprFact::illegalOpr, (CodeEmitInfo*) NULL, type)
+#else
+ : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*) NULL)
+ , _cond(cond)
+ , _type(type)
+#endif
, _label(lbl)
, _block(NULL)
, _ublock(NULL)
@@ -1690,14 +1727,14 @@ class LIR_OpBranch: public LIR_Op2 {
// for unordered comparisons
LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock);
- LIR_Condition cond() const {
- return condition();
- }
-
- void set_cond(LIR_Condition cond) {
- set_condition(cond);
- }
-
+#ifdef RISCV
+ LIR_Condition cond() const { return condition(); }
+ void set_cond(LIR_Condition cond) { set_condition(cond); }
+#else
+ LIR_Condition cond() const { return _cond; }
+ void set_cond(LIR_Condition cond) { _cond = cond; }
+#endif
+ BasicType type() const { return _type; }
Label* label() const { return _label; }
BlockBegin* block() const { return _block; }
BlockBegin* ublock() const { return _ublock; }
@@ -1775,6 +1812,7 @@ class LIR_Op3: public LIR_Op {
virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
};
+#ifdef RISCV
class LIR_Op4: public LIR_Op {
friend class LIR_OpVisitState;
protected:
@@ -1832,6 +1870,7 @@ class LIR_Op4: public LIR_Op {
virtual void print_instr(outputStream* out) const PRODUCT_RETURN;
};
+#endif
//--------------------------------
class LabelObj: public CompilationResourceObj {
@@ -2229,10 +2268,16 @@ class LIR_List: public CompilationResourceObj {
void cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info);
void cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info);
+#ifdef RISCV
void cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type,
LIR_Opr cmp_opr1 = LIR_OprFact::illegalOpr, LIR_Opr cmp_opr2 = LIR_OprFact::illegalOpr) {
append(new LIR_Op4(lir_cmove, condition, src1, src2, cmp_opr1, cmp_opr2, dst, type));
}
+#else
+ void cmove(LIR_Condition condition, LIR_Opr src1, LIR_Opr src2, LIR_Opr dst, BasicType type) {
+ append(new LIR_Op2(lir_cmove, condition, src1, src2, dst, type));
+ }
+#endif
void cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
LIR_Opr t1, LIR_Opr t2, LIR_Opr result = LIR_OprFact::illegalOpr);
diff --git a/src/hotspot/share/c1/c1_LIRAssembler.cpp b/src/hotspot/share/c1/c1_LIRAssembler.cpp
index 42a0350f7d9..68aec26c1e5 100644
--- a/src/hotspot/share/c1/c1_LIRAssembler.cpp
+++ b/src/hotspot/share/c1/c1_LIRAssembler.cpp
@@ -709,6 +709,12 @@ void LIR_Assembler::emit_op2(LIR_Op2* op) {
comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
break;
+#ifndef RISCV
+ case lir_cmove:
+ cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type());
+ break;
+#endif
+
case lir_shl:
case lir_shr:
case lir_ushr:
@@ -772,6 +778,7 @@ void LIR_Assembler::emit_op2(LIR_Op2* op) {
}
}
+#ifdef RISCV
void LIR_Assembler::emit_op4(LIR_Op4* op) {
switch(op->code()) {
case lir_cmove:
@@ -783,6 +790,7 @@ void LIR_Assembler::emit_op4(LIR_Op4* op) {
break;
}
}
+#endif
void LIR_Assembler::build_frame() {
_masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
diff --git a/src/hotspot/share/c1/c1_LIRAssembler.hpp b/src/hotspot/share/c1/c1_LIRAssembler.hpp
index c677bd346fc..baeb4aa4427 100644
--- a/src/hotspot/share/c1/c1_LIRAssembler.hpp
+++ b/src/hotspot/share/c1/c1_LIRAssembler.hpp
@@ -190,7 +190,9 @@ class LIR_Assembler: public CompilationResourceObj {
void emit_op1(LIR_Op1* op);
void emit_op2(LIR_Op2* op);
void emit_op3(LIR_Op3* op);
+#ifdef RISCV
void emit_op4(LIR_Op4* op);
+#endif
void emit_opBranch(LIR_OpBranch* op);
void emit_opLabel(LIR_OpLabel* op);
void emit_arraycopy(LIR_OpArrayCopy* op);
@@ -223,8 +225,12 @@ class LIR_Assembler: public CompilationResourceObj {
void volatile_move_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info);
void comp_mem_op(LIR_Opr src, LIR_Opr result, BasicType type, CodeEmitInfo* info); // info set for null exceptions
void comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr result, LIR_Op2* op);
+#ifdef RISCV
void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type,
LIR_Opr cmp_opr1 = LIR_OprFact::illegalOpr, LIR_Opr cmp_opr2 = LIR_OprFact::illegalOpr);
+#else
+ void cmove(LIR_Condition code, LIR_Opr left, LIR_Opr right, LIR_Opr result, BasicType type);
+#endif
void call( LIR_OpJavaCall* op, relocInfo::relocType rtype);
void ic_call( LIR_OpJavaCall* op);
void vtable_call( LIR_OpJavaCall* op);
diff --git a/src/hotspot/share/c1/c1_LinearScan.cpp b/src/hotspot/share/c1/c1_LinearScan.cpp
index c1de495260b..512b63c7445 100644
--- a/src/hotspot/share/c1/c1_LinearScan.cpp
+++ b/src/hotspot/share/c1/c1_LinearScan.cpp
@@ -1242,11 +1242,16 @@ void LinearScan::add_register_hints(LIR_Op* op) {
break;
}
case lir_cmove: {
+#ifdef RISCV
assert(op->as_Op4() != NULL, "lir_cmove must be LIR_Op4");
LIR_Op4* cmove = (LIR_Op4*)op;
+#else
+ assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
+ LIR_Op2* cmove = (LIR_Op2*)op;
+#endif
LIR_Opr move_from = cmove->in_opr1();
- LIR_Opr move_to = cmove->result_opr();
+ LIR_Opr move_to = cmove->result_opr();
if (move_to->is_register() && move_from->is_register()) {
Interval* from = interval_at(reg_num(move_from));
@@ -6296,14 +6301,23 @@ void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
// There might be a cmove inserted for profiling which depends on the same
// compare. If we change the condition of the respective compare, we have
// to take care of this cmove as well.
+#ifdef RISCV
LIR_Op4* prev_cmove = NULL;
+#else
+ LIR_Op2* prev_cmove = NULL;
+#endif
for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
prev_op = instructions->at(j);
// check for the cmove
if (prev_op->code() == lir_cmove) {
+#ifdef RISCV
assert(prev_op->as_Op4() != NULL, "cmove must be of type LIR_Op4");
prev_cmove = (LIR_Op4*)prev_op;
+#else
+ assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
+ prev_cmove = (LIR_Op2*)prev_op;
+#endif
assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
}
if (prev_op->code() == lir_cmp) {
diff --git a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp
index f36dd612eff..125cc169bea 100644
--- a/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp
+++ b/src/hotspot/share/gc/z/c1/zBarrierSetC1.cpp
@@ -100,7 +100,11 @@ class LIR_OpZLoadBarrierTest : public LIR_Op {
public:
LIR_OpZLoadBarrierTest(LIR_Opr opr) :
+#ifdef RISCV
LIR_Op(lir_zloadbarrier_test, LIR_OprFact::illegalOpr, NULL),
+#else
+ LIR_Op(),
+#endif
_opr(opr) {}
virtual void visit(LIR_OpVisitState* state) {
diff --git a/src/hotspot/share/runtime/synchronizer.cpp b/src/hotspot/share/runtime/synchronizer.cpp
index 434826853ee..e7b32723e47 100644
--- a/src/hotspot/share/runtime/synchronizer.cpp
+++ b/src/hotspot/share/runtime/synchronizer.cpp
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 1998, 2022, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1998, 2018, Oracle and/or its affiliates. All rights reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This code is free software; you can redistribute it and/or modify it