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8294187: RISC-V: Unify all relocations for the backend into AbstractAssembler::relocate() #24

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merged 1 commit into from Mar 27, 2023
Merged

8294187: RISC-V: Unify all relocations for the backend into AbstractAssembler::relocate() #24

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2 changes: 1 addition & 1 deletion src/hotspot/cpu/riscv/assembler_riscv.cpp
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Expand Up @@ -215,7 +215,7 @@ void Assembler::ret() {
void Assembler::NAME(const Address &adr, Register temp) { \
switch (adr.getMode()) { \
case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \
relocate(adr.rspec()); \
NAME(adr.target(), temp); \
break; \
} \
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10 changes: 5 additions & 5 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
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Expand Up @@ -502,7 +502,7 @@ class Assembler : public AbstractAssembler {
result_type header { \
guarantee(rtype == relocInfo::internal_word_type, \
"only internal_word_type relocs make sense here"); \
code_section()->relocate(pc(), InternalAddress(dest).rspec());
relocate(InternalAddress(dest).rspec());

// Load/store register (all modes)
#define INSN(NAME, op, funct3) \
Expand Down Expand Up @@ -547,7 +547,7 @@ class Assembler : public AbstractAssembler {
void NAME(Register Rd, const Address &adr, Register temp = t0) { \
switch (adr.getMode()) { \
case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \
relocate(adr.rspec()); \
NAME(Rd, adr.target()); \
break; \
} \
Expand Down Expand Up @@ -621,7 +621,7 @@ class Assembler : public AbstractAssembler {
void NAME(FloatRegister Rd, const Address &adr, Register temp = t0) { \
switch (adr.getMode()) { \
case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \
relocate(adr.rspec()); \
NAME(Rd, adr.target(), temp); \
break; \
} \
Expand Down Expand Up @@ -764,7 +764,7 @@ class Assembler : public AbstractAssembler {
switch (adr.getMode()) { \
case Address::literal: { \
assert_different_registers(Rs, temp); \
code_section()->relocate(pc(), adr.rspec()); \
relocate(adr.rspec()); \
NAME(Rs, adr.target(), temp); \
break; \
} \
Expand Down Expand Up @@ -807,7 +807,7 @@ class Assembler : public AbstractAssembler {
void NAME(FloatRegister Rs, const Address &adr, Register temp = t0) { \
switch (adr.getMode()) { \
case Address::literal: { \
code_section()->relocate(pc(), adr.rspec()); \
relocate(adr.rspec()); \
NAME(Rs, adr.target(), temp); \
break; \
} \
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/riscv/c1_CodeStubs_riscv.cpp
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Expand Up @@ -42,7 +42,7 @@
void C1SafepointPollStub::emit_code(LIR_Assembler* ce) {
__ bind(_entry);
InternalAddress safepoint_pc(__ pc() - __ offset() + safepoint_offset());
__ code_section()->relocate(__ pc(), safepoint_pc.rspec());
__ relocate(safepoint_pc.rspec());
__ la(t0, safepoint_pc.target());
__ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset()));

Expand Down
10 changes: 0 additions & 10 deletions src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.cpp
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Expand Up @@ -2147,16 +2147,6 @@ void LIR_Assembler::typecheck_lir_store(LIR_OpTypeCheck* op, bool should_profile
__ bind(done);
}

void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
_masm->code_section()->relocate(adr, relocInfo::poll_type);
int pc_offset = code_offset();
flush_debug_info(pc_offset);
info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
if (info->exception_handlers() != NULL) {
compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
}
}

void LIR_Assembler::type_profile(Register obj, ciMethodData* md, Register klass_RInfo, Register k_RInfo,
ciProfileData* data, Label* success, Label* failure,
Label& profile_cast_success, Label& profile_cast_failure) {
Expand Down
2 changes: 0 additions & 2 deletions src/hotspot/cpu/riscv/c1_LIRAssembler_riscv.hpp
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Expand Up @@ -58,8 +58,6 @@ friend class ArrayCopyStub;
ciMethodData *md, ciProfileData *data,
Register recv, Label* update_done);

void add_debug_info_for_branch(address adr, CodeEmitInfo* info);

void casw(Register addr, Register newval, Register cmpval);
void caswu(Register addr, Register newval, Register cmpval);
void casl(Register addr, Register newval, Register cmpval);
Expand Down
2 changes: 1 addition & 1 deletion src/hotspot/cpu/riscv/c2_safepointPollStubTable_riscv.cpp
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Expand Up @@ -39,7 +39,7 @@ void C2SafepointPollStubTable::emit_stub_impl(MacroAssembler& masm, C2SafepointP

__ bind(entry->_stub_label);
InternalAddress safepoint_pc(masm.pc() - masm.offset() + entry->_safepoint_offset);
masm.code_section()->relocate(masm.pc(), safepoint_pc.rspec());
masm.relocate(safepoint_pc.rspec());
__ la(t0, safepoint_pc.target());
__ sd(t0, Address(xthread, JavaThread::saved_exception_pc_offset()));
__ far_jump(callback_addr);
Expand Down
17 changes: 7 additions & 10 deletions src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
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Expand Up @@ -734,14 +734,13 @@ void MacroAssembler::la(Register Rd, const address &dest) {
}

void MacroAssembler::la(Register Rd, const Address &adr) {
code_section()->relocate(pc(), adr.rspec());
relocInfo::relocType rtype = adr.rspec().reloc()->type();

switch (adr.getMode()) {
case Address::literal: {
relocInfo::relocType rtype = adr.rspec().reloc()->type();
if (rtype == relocInfo::none) {
li(Rd, (intptr_t)(adr.target()));
} else {
relocate(adr.rspec());
movptr(Rd, adr.target());
}
break;
Expand Down Expand Up @@ -1361,7 +1360,7 @@ void MacroAssembler::reinit_heapbase() {

void MacroAssembler::mv(Register Rd, Address dest) {
assert(dest.getMode() == Address::literal, "Address mode should be Address::literal");
code_section()->relocate(pc(), dest.rspec());
relocate(dest.rspec());
movptr(Rd, dest.target());
}

Expand Down Expand Up @@ -2734,7 +2733,7 @@ void MacroAssembler::la_patchable(Register reg1, const Address &dest, int32_t &o
assert(is_valid_riscv64_address(dest.target()), "bad address");
assert(dest.getMode() == Address::literal, "la_patchable must be applied to a literal address");

code_section()->relocate(pc(), dest.rspec());
relocate(dest.rspec());
// RISC-V doesn't compute a page-aligned address, in order to partially
// compensate for the use of *signed* offsets in its base+disp12
// addressing mode (RISC-V's PC-relative reach remains asymmetric
Expand Down Expand Up @@ -3016,7 +3015,7 @@ void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype)
// Read the polling page. The address of the polling page must
// already be in r.
void MacroAssembler::read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype) {
code_section()->relocate(pc(), rtype);
relocate(rtype);
lwu(zr, Address(r, offset));
}

Expand All @@ -3031,8 +3030,7 @@ void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
}
#endif
int oop_index = oop_recorder()->find_index(obj);
RelocationHolder rspec = oop_Relocation::spec(oop_index);
code_section()->relocate(pc(), rspec);
relocate(oop_Relocation::spec(oop_index));
li32(dst, 0xDEADBEEF);
zero_extend(dst, dst, 32);
}
Expand All @@ -3043,9 +3041,8 @@ void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
int index = oop_recorder()->find_index(k);
assert(!Universe::heap()->is_in(k), "should not be an oop");

RelocationHolder rspec = metadata_Relocation::spec(index);
code_section()->relocate(pc(), rspec);
narrowKlass nk = CompressedKlassPointers::encode(k);
relocate(metadata_Relocation::spec(index));
li32(dst, nk);
zero_extend(dst, dst, 32);
}
Expand Down