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8291550: RISC-V: jdk uses misaligned memory access when AvoidUnalignedAccess enabled #1852
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👋 Welcome back omikhaltcova! A progress list of the required criteria for merging this PR into |
This backport pull request has now been updated with issue from the original commit. |
@@ -4099,7 +4185,8 @@ address MacroAssembler::zero_words(Register ptr, Register cnt) { | |||
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// base: Address of a buffer to be zeroed, 8 bytes aligned. | |||
// cnt: Immediate count in HeapWords. | |||
void MacroAssembler::zero_words(Register base, u_int64_t cnt) { |
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looks like this edit was accidentially added to the backport, other than that - looks good
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Thx! That's right, this line break was inserted by mistake. Fixed.
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@omikhaltsova This change now passes all automated pre-integration checks. ℹ️ This project also has non-automated pre-integration requirements. Please see the file CONTRIBUTING.md for details. After integration, the commit message for the final commit will be:
You can use pull request commands such as /summary, /contributor and /issue to adjust it as needed. At the time when this comment was updated there had been 18 new commits pushed to the
As there are no conflicts, your changes will automatically be rebased on top of these commits when integrating. If you prefer to avoid this automatic rebasing, please check the documentation for the /integrate command for further details. ➡️ To integrate this PR with the above commit message to the |
/integrate |
Going to push as commit adef8e4.
Your commit was automatically rebased without conflicts. |
@omikhaltsova Pushed as commit adef8e4. 💡 You may see a message that your pull request was closed with unmerged commits. This can be safely ignored. |
I'd like to backport JDK-8291550 to jdk17u. This fix is related only to RISC-V.
The patch applies not cleanly. It differs from the original one in the following:
1. src/hotspot/cpu/riscv/c2_MacroAssembler_riscv.cpp
#undef VFCVT_SAFE
was removed because there is no#define VFCVT_SAFE(VFLOATCVT)
(JDK-8306966)2. src/hotspot/cpu/riscv/gc/shared/barrierSetNMethod_riscv.cpp
The difference is in context due to method signature change by JDK-8299229
void NativeNMethodBarrier::verify() const {..
bool NativeNMethodBarrier::check_barrier(err_msg& msg) const {..
msg.print(..)
was replaced withtty->print_cr(..)
3. src/hotspot/cpu/riscv/interp_masm_riscv.cpp
The changes were not applied to
void InterpreterMacroAssembler::load_resolved_indy_entry(Register cache, Register index) {
This method doesn't exist, it was added by JDK-8301995.
4. src/hotspot/cpu/riscv/macroAssembler_riscv.cpp
The difference is in context due to the method signature change by JDK-8298075
address MacroAssembler::get_target_of_li32(address insn_addr) {
static address get_target_of_li32(address insn_addr)
{NULL
was replaced withnullptr
by JDK-8301496.5. src/hotspot/cpu/riscv/nativeInst_riscv.cpp
src/hotspot/cpu/riscv/nativeInst_riscv.hpp
NULL
was replaced withnullptr
by JDK-8301496Testing: tier1 tests successfully passed on a RISC-V HiFive board with Linux.
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$ git fetch https://git.openjdk.org/jdk17u-dev.git pull/1852/head:pull/1852
$ git checkout pull/1852
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$ git checkout pull/1852
$ git pull https://git.openjdk.org/jdk17u-dev.git pull/1852/head
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$ git pr checkout 1852
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https://git.openjdk.org/jdk17u-dev/pull/1852.diff
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